Learning Outcome

1. EEE2243Digital System DesignChapter 3: Verilog HDL (Combinational)by Muhazam Mustapha, January 2011

2. Learning Outcome • By the end of this chapter, students are expected to be able to: • Quartus II • Verilog

3. Chapter Content • Why HDL? • Verilog • Boolean Equation Modeling • Behavior Modeling

4. Why HDL?

5. Hardware Description Language • A drawing of a circuit, or schematic, contains graphical information about a design • Inverter is above the OR gate, AND gate is to the right, etc. • Such graphical information may not be useful for large designs • Can use textual language instead D oorOpener c f h p Vahid Slide

6. Hardware Description Language Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL –Defined in 1980s by U.S. military; Ada-like language Verilog –Defined in 1980s by a company; C-like language SystemC –Defined in 2000s by several companies; consists of libraries in C++ Vahid Slide

7. Verilog

8. General Structure modulemodule_name(ports) { parameterdeclaration } inputport_list; outputport_list; wirelist; reg (or integer) list; { assigncontinuous_statement; } { initialblock; } { alwaysblock; } { gate instantiations; } { module instantiations; } endmodule Mohamed Khalil Hani

9. General Structure • Example: module CircuitA(Cin, x, y, X, Y, Cout, s, Bus, S) input Cin, x, y; input [3:0] X, Y; output Cout, s; output [3:0] S; inout [7:0] Bus; wire d; reg e; ... endmodule Mohamed Khalil Hani

10. Constant Representation • Format: <size_in_bit>’<base_id><significant_digit> • Example: 8 bit binary: 8’b0011101012 bit hex: 12’habc7 bit decimal: 7’d50 • Negative numbers are internally represented as 2’s complement, but in the code we just use signed magnitude: Negative 5 bit binary: -5’b01010Negative 8 bit hex: -8’h8c Mohamed Khalil Hani

11. Constant Representation • High-Z output is represented as z • Undefined output is represented as x 8 bit binary with 4 bit z: 8’bzzzz10108 bit binary with 4 bit x: 8’b1010xxxx Mohamed Khalil Hani

12. Operators Mohamed Khalil Hani

13. Modeling Style There are 3 coding styles in Verilog Boolean Equation Done by writing Verilog version of Boolean equation to define output Behavioral Done by writing the output arithmetical definition instead of the direct Boolean equation Structural Done writing Verilog in multiple modules We will first cover Boolean equation and Behavioral Mohamed Khalil Hani

14. Boolean Equation Modeling

15. assign Keyword The pure Boolean combinational style modeling is signified by the use of assign keyword module functionA(x1, x2, x3, f); input x1, x2, x3; output f; assign f = (~x1 & ~x2 & x3) | (x1 & ~x2 & ~x3) | (x1 & ~x2 & x3) | (x1 & x2 & ~x3);endmodule x1 Logic Function x2 f x3 Mohamed Khalil Hani

16. Example – AND Gate module ANDGate(x, y, f); input x, y; output f; assign f = x & y;endmodule x f y Quartus II version 9 Demo

17. Example – Boolean Half Adder module HalfAdder(a, b, sum, carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b;endmodule x1 sum carry x2 Quartus II version 9 Demo Mohamed Khalil Hani

18. Behavior Modeling

19. always Keyword The behavioral style modeling is signified by the use of always keyword Many C-like keywords can also be used For a complex design, behavioral style is more favorable module ORGate(x, y, f); input x, y; output f; reg f; always@(x or y) begin if (x == 0) && (y == 0) f = 0; else f = 1; endendmodule Mohamed Khalil Hani Also read Vahid pg 496

20. Example – Behavioral Half Adder module HalfAdder(a, b, sum_carry); input a, b; output [1:0] sum_carry; reg [1:0] sum_carry; always@(a or b) begin sum_carry = a + b; endendmodule Quartus II version 9 Demo