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RMO1C-3

RMO1C-3. An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio. Emanuel Cohen (12) , Shmuel Ravid (1) , and Dan Ritter (2) Mobile Wireless Group, Intel Haifa, Israel Department of Electrical Engineering, Technion, Haifa, Israel. Outline.

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RMO1C-3

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  1. RMO1C-3 An ultra low power LNA with 15dB gain and 4.4db NF in 90nm CMOS process for 60 GHz phase array radio • Emanuel Cohen(12), Shmuel Ravid(1), and Dan Ritter(2) • Mobile Wireless Group, Intel Haifa, Israel • Department of Electrical Engineering, Technion, Haifa, Israel RFIC – Atlanta June 15-17, 2008

  2. Outline • Design methodology flow and passives • Circuit implementation options • LNA measurements • Conclusions RFIC – Atlanta June 15-17, 2008

  3. Motivation • How low can we get power consumption in a mm-wave LNA without compromising gain NF and size? • Typical LNA designed for 60GHz showed a power of 20mW (@15dB gain). For a phase array with 30-60 elements we end up with ~1Watt ! • Power and size must go down for a full phase array system in commercial application RFIC – Atlanta June 15-17, 2008

  4. LNA Design Methodology • Choose the passive circuits and models • Choose the transistor width for optimized target • Choose best topology with optimized transistor width RFIC – Atlanta June 15-17, 2008

  5. Passive inductor design • Ground ring on inductor improves isolation by 19dB • No real impact on Q RFIC – Atlanta June 15-17, 2008

  6. Creating inductor simple model • Build a model based on a library of inductors with EM simulation • Then the design can be optimized without EM iterations Simple pi model RFIC – Atlanta June 15-17, 2008

  7. Full EM simulation • Full EM possible in momentum - 8 hour run • Excellent fit to stand alone inductor  proves good inductor isolation with ground ring RFIC – Atlanta June 15-17, 2008

  8. Capacitors Finger Cap MIM cap 200pf Parasitic capacitance [pf] Q Parasitic capacitance [pf] [pf] Q • MIM cap Q~9 and finger cap Q >>10 • Finger cap has ~8% parasitic (after optimizing and using 2-4 layers only) • Finger cap was chosen for the design RFIC – Atlanta June 15-17, 2008

  9. Transistor size and circuit topology • Transistor size is the key issue for low power design For Q~20 • 0.3dB max penalty , with full simulation even less • ¼ of power consumption RFIC – Atlanta June 15-17, 2008

  10. LNA behavior with W change No real BW degradation Different Transistors Have similar Q impedance • 3 stage CSdesign with different transistor sizes • and same current density. • Similar performance is achieved with W=10um and 3x10um RFIC – Atlanta June 15-17, 2008

  11. LNA with different topologies • Using optimized flow to check different topologies without iterations • All topologies designed for ~4mW W=1x10um RFIC – Atlanta June 15-17, 2008

  12. Low Noise Amplifier schematic • Big inductors still maintain high SRF • Have better Q RFIC – Atlanta June 15-17, 2008

  13. LNA Layout • die 440 um x 320 um • Size limited by pads- inner core (0.04mm2) RFIC – Atlanta June 15-17, 2008

  14. Measured and Simulated Performance • Gmax=15dB NF=4.4dB • Power consumption 4mW RFIC – Atlanta June 15-17, 2008

  15. NF set-up at 60Ghz Down converter NFA [ S. Pellerano, Y. Palaskas , K. Soumyanath “A 64GHz 6.5dB NF 15.5dB Gain LNA in 90nm CMOS” in IEEE ESSCIRC 2007 ] RFIC – Atlanta June 15-17, 2008

  16. Comparison with State of the Art LNAs • Lowest power with smallest size at same Gain RFIC – Atlanta June 15-17, 2008

  17. Additional bias point characterization • Bias point compromise • 0.2dB in NF • 3dB in Gain RFIC – Atlanta June 15-17, 2008

  18. NF , Gain vs. total power dissipation • Maximum points align on the same line • There is no difference between changing Vds or Ids • Consumption can drop to 2mW for 12dB of gain RFIC – Atlanta June 15-17, 2008

  19. Compression point measure • Max input signal ~ -25dBm for high data rates • This is enough for a 60Ghz link budget RFIC – Atlanta June 15-17, 2008

  20. Conclusions • Fast design flow with lumped inductor and ground ring was created • The flow enabled a check of full circuits topology for a fair comparison on optimized results • The CS and small transistor size 1x10um is the best tradeoff between power consumption Gain and NF. • A record power consumption of 4mW achieved with best NF of 4.4dB 15dB gain and similar to smallest footprint published • Lumped inductor enabled smallest size and no additional design complexity RFIC – Atlanta June 15-17, 2008

  21. Thank You RFIC – Atlanta June 15-17, 2008

  22. Input impedance with W • Q is very similar 10um 40um RFIC – Atlanta June 15-17, 2008

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