WP2 Review Meeting Milan, October 05, 2011

1. MODERN ENIAC WP2 Meeting (WP2-T2.4) WP2 and Tasks review Milano Agrate, 2011 Oct. 05 Meeting hosted by Micron WP2 Review Meeting Milan, October 05, 2011

2. Relation among Work Packages WP2 Review Meeting Milan, October 05, 2011 2

3. T2.4 Task (1/2) Task T2.4: Correlation between PV and reliability, reliability modeling The impact of process variability on existing device reliability degradation models will be clarified. Aging measure-ments will be performed on test structures: Device degradation mechanisms will be identified based on silicon, their effect on PV parameters will be characterized and modeled to allow for a better description of aging during operation. Partners: AMS, IMEP, UNET, TUW, UNCA, UNGL UNGL will develop methodologies for the simulation of the statistical impact of NBTI and hot carrier degradation on the MOSFET characteristics in concert with the statistical variability sources described in T2.2 and its capture in statistical compact models. UNCA will perform aging measurements on nano-MOSFET devices focusing on the three main reliability mechanisms: hot-carrier injection, bias-temperature instability and time-dependent dielectric breakdown. The impact of process variation (e.g. line edge roughness, random dopant distribution, non-homogenity of the gate dielectric) on the device reliability will be investigated and potential solutions will be proposed. Aging models will be developed to predict device lifetime dependence on the statistical fluctuations of geometrical and technological parameters of nano-MOSFET. Model parameters will be calibrated with the hardware results of aging measurements. UNET will work on methodologies to design reliability experiments that allow characterizing the impact of PV on test structures, single cells or simple arrays, on 45nm & 32nm planar CMOS, and on Non-Volatile Memories. It will include the development of compact models including aging effects. AMS will execute lifetime measurements necessary for model development and the usage in SPICE simulators in 0.13um, 0.18um and 0.35um CMOS and HV technologies. The objective is to develop silicon based models for PV and reliability correlation. Lifetime measurements will be performed on appropriate test structures. Based on that data set, PV-aware parameter degradation models for NBTI and HCI effects will be developed at TUW. Since in particular degradation caused by NBTI is known to recover quickly once the stress is removed, emphasis will be put on a proper description of the dynamical properties of the degradation. 3 WP2 Review Meeting Milan, October 05, 2011

4. T2.4 Task (2/2) Task T2.4: Correlation between PV and reliability, reliability modeling (cont’) With future technology nodes it is becoming more and more critical to consider statistical and deterministic variations for ensuring the design goal at time of manufacturing as well as for the proposed lifetime. IMEP will investigate based on mixed mode TCAD simulation and on analytical models the SBD/BD failure occurrence impact at device level on device characteristics and at elementary circuit level on subsequent circuit functioning. These studies will be extended to new device architecture featuring thin silicon film (MugFET, GAA), which will be benchmarked in term of reliability robustness to bulk devices. This will require a detailed analysis of the SBD/BD occurrence and characterization on actual FD-SOI or GAA devices. The work will be carried out in collaboration with STF2. 4 WP2 Review Meeting Milan, October 05, 2011

5. Reliability: T2.4 Deliverables Task Leader: Jong-mun.park@austriamicrosystems.com  5 WP2 Review Meeting Milan, October 05, 2011

6. D2.4.1 Considered degradation effects Contributions 6 WP2 Review Meeting Milan, October 05, 2011

7. D2.4.1 Measurements Contributions 7 WP2 Review Meeting Milan, October 05, 2011

8. D2.4.1 Modeling approach 8 WP2 Review Meeting Milan, October 05, 2011

9. T2.4 Review Summary (1/2) Activitydoneso far, withhighlights on technicalresults, and dissemination - D2.4.1 deliverable: done - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations (AMS & TUW), LV NMOS & PMOS (GOX:15 nm), 20V nLDMOS & pLDMOS (GOX: 7 nm) - Discuss with T2.5 the most interesting devices for the demonstrator, with T2.1 the process parameters to take into account. (All T2.4 members) - Initial physics-based analytical model for NBTI to implement in circuit simulator (UNGL) - Survey of degradation effects (TUW, UGLA) - Time dependent modeling of degradation for NBTI & HC (TUW, back-up slides) D2.4.2 deliverable (M24): Done - TCAD reliability simulations focused on LV devices in HV-CMOS process. - Hot-carrier degradation measurements for analytical & TCAD model developments. - Threshold Voltage MismatchInduced by Hot-Carrier in 65 and 45 nm TechnologyNode. 9 WP2 Review Meeting Milan, October 05, 2011

10. T2.4 ReviewSummary (2/2) Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI (UNGL). - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. (UNGL) - Analytical NBTI and HC model developments for LV- & HV-CMOS - TCAD reliability simulations focused on HV-CMOS technology(AMS, TUW) - Digital IG noise simulation (UNET) - All T2.4 members Issues : Interaction need: - AMS & TUW: 0.35 µm LV-CMOS & HV-CMOS, D2.4.2 and D2.4.3 (output for T2.5) - UNET (partner: NMX): NVM, D2.4.2 and D2.4.3 - UNCA (partner: ST-I): 65 nm, D2.4.2 and D2.4.3 - UNGL (partner: STF2): 45 nm CMOS, D2.4.3 - IMEP (partner: STF2): Finfets, MUG, GAA, D2.4.3 10 WP2 Review Meeting Milan, October 05, 2011

11. T2.4 Back-up slides • NBTI & Hot-Carrier Activities (TUW) • SubthresholdSlopeMismatchInduced by Hot-Carrier in 65 and 45 nm TechnologyNode (UNCA & NXP) • Digital IG Noise Simulations (UNET) • A Methodology for Simulating the Statistical Aspect of P/NBTI and Hot-Carrier Degradation (UNGL) • Hot-Carrier Lifetime Models for High-Voltage Transistors (AMS) 11 WP2 Review Meeting Milan, October 05, 2011

12. 1. NBTI & Hot-Carrier Activities( D2.4.3)Vienna Universty of Technology (TUW) 12 WP2 Review Meeting Milan, October 05, 2011

13. Present/Done Activities: NBTI • Discrete capture/emission time map (CET) of τc and τe • Strong bias dependence of τc • Strong temperature dependence of both τc and τe • Note: τc = τc(VH) and τc = τc(VL) 13 WP2 Review Meeting Milan, October 05, 2011

14. Present/Done Activities: NBTI • What is the use of CET time map? • Reconstruct the temporal behavior (jus like Fourier transform) • Macroscopic version (expectation value) • Example CET map for an SiONpMOS with EOT = 2.2 nm 14 WP2 Review Meeting Milan, October 05, 2011

15. Present/Done Activities: NBTI • Analytical model for the CET map • Two bivariate normal distributions for the activation energies • Parameters bias-dependent 15 WP2 Review Meeting Milan, October 05, 2011

16. Present/Done Activities: NBTI • Analytical model for the CET map • Allow analytical integration for DC and AC stress 16 WP2 Review Meeting Milan, October 05, 2011

17. Present/Done Activities: NBTI • Examples for analytical NBTI model • Verified for SiO2, SiON, HfSiO, and HfSiON 17 WP2 Review Meeting Milan, October 05, 2011

18. Future Activities: NBTI • Distribution of activation energies • Microscopic origin of the effective activation energy distribution • Must be linked to microscopic defect model 18 WP2 Review Meeting Milan, October 05, 2011

19. Present/Done Activities: HCD • The model Features of previous approaches Linking all the levels related to this effect • A physics-based model contains Carrier transport module Module describing the defect build-up Module for simulation degraded devices • Carrier transport Full-band Monte-Carlo device simulator MONJU Allows to thoroughly evaluate the DF For a particular device architecture 19 WP2 Review Meeting Milan, October 05, 2011

20. Present/Done Activities: HCD • The linear drain current degradation • Idlin0 – current in a “fresh” device, ΔIdlin – its change • Vt – threshold voltage, ΔVt – its shift • μ0 – mobility of a “fresh” device, Δμ – mobility change • Mobility degraded due to Nit • αsc– prefactor • ΔVt ≈ 0 in our devices A. Bravaixet al., IRPS-2009 N. Stojadinovicet al., Electron Lett., 1995 20 WP2 Review Meeting Milan, October 05, 2011

21. Present/Done Activities: HCD • Analytical approach to HCD modeling • Based on the TCAD version • Incorporates interplay between single- and multiple-carrier processes for Si-H bond-breakage • Controlled by the carrier acceleration integral (AI) • Average Nit,SE is introduced • Analytical expression for I(x) Integratable Average Nit→ analytical 21 WP2 Review Meeting Milan, October 05, 2011

22. Present/Done Activities: HCD • Slopes of the AI peak • described by Fermi-Dirac derivatives • on a log-scale • piecewise functions • Parameters varying with Vds: • slope of I2: β • extension of the ledge I4: x4-x3 • heights: A2, A3, A4 22 WP2 Review Meeting Milan, October 05, 2011

23. Present/Done Activities: HCD • Parameters vs. Vds • linear dependence on Vds • scattering in parameters: • stochastic noise • from TCAD model • based on Monte-Carlo • Dependences: • useful to interpolate values • and calculate AI • instead of time-consuming • Monte-Carlo method Analyze impact of statistical variations on HCD 23 WP2 Review Meeting Milan, October 05, 2011

24. Present/Done Activities: HCD • Average Nit concentration: • contains components Ji related to Ii • expressed via exponential integrals • explicit expressions for Ji: 24 WP2 Review Meeting Milan, October 05, 2011

25. Present/Done Activities: HCD • Representation of the SE-component • TCAD results ↔ experiment • Damage produced by the SE-mechanism • Good agreement between TCAD and analytical models 25 WP2 Review Meeting Milan, October 05, 2011

26. Present/Done Activities: HCD • SE- and ME-contributions are now considered • Rather good agreement between: • experiment • TCAD model results • analytical model results 26 WP2 Review Meeting Milan, October 05, 2011

27. Future Activities: HCD Model • Oxide thickness varies: • Tox = 0.4, 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, 1.9 Tn • Tn – nominal thickness 27 WP2 Review Meeting Milan, October 05, 2011

28. 2. SubthresholdSlopeMismatchInduced by Hot-Carrier in 65 and 45 nm TechnologyNode(Ref.: D2.4.2)Universty of Calabria (UNCA)in collaboration with NXP 28 WP2 Review Meeting Milan, October 05, 2011

29. PURPOSE To characterize and to model the HC-induced subthreshold slope variability in 65 nm and 45 nm technology node 29 WP2 Review Meeting Milan, October 05, 2011

30. Devices Under Test The reported statistical analysis is based on a large overall sample population of one thousand transistors 30 WP2 Review Meeting Milan, October 05, 2011

31. Modeling of HC-indicedSubthresholdSlopeVariability HC stress causes an increase in the interface state density Dit and thus in the interface capacity Cit which induces a change in S Defectdepassivationisassumed to be a Poissonprocess KHC parameter takes into account for the non-uniform defect depassivation along the channel direction 31 WP2 Review Meeting Milan, October 05, 2011

32. Model Suitability Experimental data are well fitted by the proposed model, where median DS is used as an input and KHC is extrapolated by interpolation of experimental data The slope of this plot is very close to 0.5, hence confirming the hypothesis of Poisson process 32 WP2 Review Meeting Milan, October 05, 2011

33. Impact of the HC-InducedVariability on the OverallVariability A significantincrease of the overallDSmismatchisobserved for bothtechnologies 33 WP2 Review Meeting Milan, October 05, 2011

34. Correlationbetween VT and S Correlation coefficient is around 0.5 for both technologies 34 WP2 Review Meeting Milan, October 05, 2011

35. 3. Digital IG noise simulations (D2.4.3) Consorzio Nazionale Interuniversitario per la Nanoelettronica (UNET) 35 WP2 Review Meeting Milan, October 05, 2011

36. Digital IG Noise Simulations • Physical model reproducingdigital IG fluctuations observed inultra-thin dielectrics after SBD • Current fluctuations are modeledassuming that some traps in thepercolation path switch betweentwo unstable configurations,corresponding to neutral andnegatively charged O vacancies. Ref: L. Morassi et al, “ A Physical Model for post-breakdown digital gate current noise,” submitted to IEEE Electron Device Letters, 2011 36 WP2 Review Meeting Milan, October 05, 2011

37. 4. A Methodology for Simulating the Statistical Aspect of P/NBTI and Hot-Carrier Degradation ( D2.4.3) The University of Glasgow (UNGL) 37 WP2 Review Meeting Milan, October 05, 2011

38. Purpose • We developed a methodology for simulating the statistical aspect of P/NBTI and hot carrier degradation in 32nm RVT N/PMOS. • Random trapped charges due to P/NBTI stress are assigned to interface degradation. • The threshold-voltage shift is observed and its variations are analyzed. 38 WP2 Review Meeting Milan, October 05, 2011

39. 3-D Simulation Method • The N/PMOS are first calibrated both in doping profiles and electrical characteristics. • After stress, the traps are randomly assigned at interface according to local nominal trap sheet density. 39 WP2 Review Meeting Milan, October 05, 2011

40. Device Degradation under Stress Under PBTI/PBTI stress, the interface trapped charge accumulates, leading to threshold-voltage shift and device performance degradation. 40 WP2 Review Meeting Milan, October 05, 2011

41. PBTI/NBTI Variability • NMOS • PMOS Both number and placement of traps varies, which leads to variation of PBTI/NBTI effects. 41 WP2 Review Meeting Milan, October 05, 2011

42. Trap Density Dependence The threshold-voltage shift is proportional to trap density and its standard deviation is proportional to the sqrt of trap density. Both are proportional to EOT. PMOS EOT is slightly larger than NMOS. 42 WP2 Review Meeting Milan, October 05, 2011

43. 5. Hot-Carrier Degradation Measurements (Ref.: D2.4.2) 0.35 µm HV-CMOS Technology - LV-NMOSI, LV-NMOSIM - NMOSI20T - PMOS20T austriamicrosystems AG 43 WP2 Review Meeting Milan, October 05, 2011

44. Proposal for a Lifetime Model for High-Voltage Devices • 1. Kirk effect: change of location of maximum impact ionisation: depending on gate-voltage. • 2. Occurance of multiple locations of significant impact ionisation: depending on bias. • 3. Electron injection, hole injection, interface trap generation simultaneously. 4. Self heating. • No generally accepted HC model is available. • Formulation of a HC model where Vg and T is an additional parameter: Modified Hu- model, empirical 44 WP2 Review Meeting Milan, October 05, 2011

45. NMOSIM: Cross Section 45 WP2 Review Meeting Milan, October 05, 2011

46. LV-NMOSIM: Transfer Curves VDS=0.1 V forLg=0.5 µm VGstress=2 V andVDstress=7 V Stress time: 1x105 sec VDS=5.0 V forLg=0.5 µm VGstress=2 V andVDstress=7 V Stress time: 1x105 sec 46 WP2 Review Meeting Milan, October 05, 2011

47. LV-NMOSIM: Output Curves, Degadation versus Stress Time Output curves VGstress=2 V andVDstress=7 V Stress time: 1x105 sec Degradation versus stress time VGstress=2 V andVDstress=7 V 47 WP2 Review Meeting Milan, October 05, 2011

48. LV-NMOSIM: Lifetime-Substrate Current, Ionization-Rate andLgEffects on theLifetime Lifetime versus substratecurrent Id x lifetime versus ionization-rate Ionization-rate andLgeffects on thelifetime 48 WP2 Review Meeting Milan, October 05, 2011

49. LV-NMOSIM: Charge Pump Measurements Time evolutionoftheIcp versus Vgh Interface statedensityatthechannelregion 49 WP2 Review Meeting Milan, October 05, 2011

50. HV-NMOS (NMOSI20T) and HV-PMOS (PMOS20T) PMOS20T NMOSI20T 50 WP2 Review Meeting Milan, October 05, 2011