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I/O STANDARDS & DESIGN

I/O STANDARDS & DESIGN. Muthukumar Nagarajan 02/29/08. AGENDA. GOAL SIGNALING STANDARDS INPUT BUFFER OUTPUT BUFFER I/O DESIGNS ESD. GOAL. A peek into the world of I/O standards and I/O buffer design Brief Introduction to Signaling (I/O) Standards Key I/O parameters

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I/O STANDARDS & DESIGN

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  1. I/O STANDARDS & DESIGN Muthukumar Nagarajan 02/29/08

  2. AGENDA • GOAL • SIGNALING STANDARDS • INPUT BUFFER • OUTPUT BUFFER • I/O DESIGNS • ESD

  3. GOAL • A peek into the world of I/O standards and I/O buffer design • Brief Introduction to Signaling (I/O) Standards • Key I/O parameters • I/O buffer designs • Analog design in I/O buffers

  4. I/O STANDARDS • WHY I/O STANDARDS • To create a common language that IC’s can use to communicate with each other and form a system to enable a solution • I/O STD ORG’s • Several governing bodies create communication protocols. The Electrical signaling standards (I/O std.) is one part of this protocol • Some well known organizations • JEDEC (LVTTL, LVCMOS, HSTL, SSTL) • TIA/EIA (LVDS, VoIP) • IEEE (802 LAN/MAN)

  5. I/O STANDARDS

  6. I/O BUFFER TYPE • SINGLE ENDED • A signal (Data or Clock) that is defined by a single port/wire/net • Signal swing is Rail-to-Rail or a small swing around a fixed reference level • DIFFERENTIAL • A signal (Data or Clock) that is defined by the difference of two signals around a common mode level • Small signal swings, High speed, Low noise

  7. INPUT BUFFER • SINGLE ENDED (CMOS) • Basically an inverter • Designed for a specific Voltage Trip Point by simply using P vs. N FET W/L ratio • DIFFERENTIAL • Basically a Diff. Amp. • Designed for a specific CM level and Input Swing • FEATURES • Hysterisis to improve Noise Immunity • Input pin ESD Protection • Buffer output to drive the Chip core • Performance requirements (High speed, Low power, Low leakage, HV tolerance etc.) dictate buffer design and complexity

  8. INPUT BUFFER: TOPOLOGIES 1

  9. INPUT BUFFER: TOPOLOGIES 2

  10. INPUT BUFFER: TOPOLOGIES 3

  11. INPUT BUFFER : KEY PARAMETERS 1 • VIH – Input HIGH Level • VIL – Input LOW Level • VHYST – Hysterisis (VIH - VIL) • VREF – Input Reference Voltage • VIPP – Peak-to-Peak Input Swing • VICM – Input Common Mode Level • FMAX – Max Frequency of operation • ISB – Leakage Power • ICC – Dynamic (Active) Power

  12. INPUT BUFFER : KEY PARAMETERS 2

  13. OUTPUT BUFFER • SINGLE ENDED (CMOS) • Basically an inverter • Designed to drive large loads (several pF) • DIFFERENTIAL • Basically a Diff. Amp. • Designed for a specific CM level and Output Swing • FEATURES • Tri-State • Output pin ESD protection • Programmable Drive strength, Slew rate • Hot Swap, HV Tolerance • Weak Pull-up, Pull-down • Signal voltage domain converter • Impedance Matching

  14. OUTPUT BUFFER: TOPOLOGIES 1

  15. OUTPUT BUFFER: TOPOLOGIES 2

  16. OUTPUT BUFFER : KEY PARAMETERS 1 • VOH – Output HIGH Level @ IOH • VOL – Output LOW Level @ IOL • IOH – Output HIGH current @ VOH • IOL - Output LOW current @ VOL • IOZ – Output pin leakage • tOR, tOF – Output Rise/Fall time • Noise (On chip Pwr/Gnd and Signal) • VOPP – Peak-to-Peak Output Swing • VOCM – Output Common Mode Level • FMAX – Max Frequency of operation • ISB – Leakage Power • ICC – Dynamic (Active) Power

  17. OUTPUT BUFFER : KEY PARAMETERS 2

  18. CY I/O DESIGN • Programmable I/O’s in PSoC • I/O Ring

  19. ESD

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