Microprocessors

1. Microprocessors May 12th, 2002

2. Introduction • Motorola controls roughly 40% of the 32-bit embedded processor market • ColdFire is the next generation 68K(research on commonly used instructions and addressing modes) • Result is a variable length RISC chip • Length varies from 1 to 3 words

3. Integer Units • 16 general purpose 32-bit registers • D0-D7: Data registers • Can be used as index registers • A0-A7: Address registers • Software stack pointers • Index registers • Base address registers • A7 is used as hardware stack pointer during stacking for subroutine calls and exception handling

4. Integer Units Cont… • 32-bit Program Counter (PC) • For some modes the PC can serve as a pointer for PC relative addressing • 8-bit Condition Code Register (CCR) • Status Register’s low order byte. Only potion of the SR available in User Mode

5. CCR

6. Floating Point Units • 8 64-bit FP data registers (FP0-FP7) • FP data registers are analogous to the integer data registers • Numbers stored in double-precision format • All external data, operands, etc are converted to double –precision before storage • A reset or a null-restore sets FP0-FP7 to positive, nonsignaling NANs

7. FPUs cont… • 32-bit FP control register (FPCR) • Next slide has bit information for FPCR • 32-bit FP status register (FPSR) • Refer to manual pages 16 and 17 for bit information • 32-bit FP instruction address register (FPIAR)

9. FPUs cont… • ColdFire can execute Integer and FP instructions simultaneously • In case of exception, PC value stacked doesn’t may not point to correct instruction • For the FPU instructions that can generate traps, the FPIAR is loaded with the PC address before FPU begins instructions

10. Optional MAC Module • Multiply and Accumulate Module • 32-bit MAC status register (MACSR) • 32-bit accumulator register (ACC) • Contains the result of MAC operations • 32-bit MAC mask register (MASK) • Only the low-order 16-bits are implemented • When loaded, the low-order 16 bits of the operand are loaded into the register. When stored, the upper 16-bits are forced to 1.

11. Optional EMAC Module • Enhanced MAC • 32-bit MACSR • Plus 4 indicator bits for product of accumulation overflow (PAV0-PAV3) • 4 32-bit accumulators (ACC0-ACC3) • 8 8-bit accumulator extensions (ACCext01, ACCext23) • See manual pages 22 and 23

12. EMAC cont… • 32-bit mask register (MASK) • Integrated EMAC provides a common set of DSP operations and enhances the Integer multiply instructions. • Provides functionality in 3 areas: 1. Faster signed and unsigned integer multiplies 2. New multiply-accumulate operations supporting signed and unsigned operands 3. New miscellaneous register operations

13. Supervisor Programming Model • Used to implement OS functions. • All accesses that affect the control features of the ColdFire processors must be made in supervisor mode. • 16-bit status register (SR) • 32-bit supervisor stack pointer (OTHER_A7) • 32-bit vector base register (VBR) • 32-bit cache control register (CACR) • 32-bit address space ID register (ASID) • 2 32-bit data access control registers (ACR0-1) • 2 32-bit instruction access control registers (ACR2-3)

14. continued… • 32-bit MMU base address register (MMUBAR) • 2 32-bit ROM base address registers (ROMBAR0-1) • 2 32-bit RAM base address registers (RAMBAR0-1) • 32-bit module base address register (MBAR) • Not all registers are implemented on every version of ColdFire (see page 24)

15. OTHER_A7 • This only exists in V4 of ColdFire • In V4, the SSP and SP exist to provide the necessary support for isolation as dictated by the virtual memory management scheme provided by the Memory Management Unit (MMU). if SR[S] = 1 then A7 = Supervisor Stack Pointer other_A7 = User Stack Pointer else A7 = User Stack Pointer other_A7 = Supervisor Stack Pointer

16. VBR (Vector Base Reg.) • Bits 0-19 are set to 0 • Bits 20-31 contains the 1MByte-aligned base address of the exception vector table in memory. CACR (Cache Control Reg.) • Controls operation of data and instruction cache memory • Bits can enable, freeze, invalidate cache • Also can define default cache mode and write-protect fields

17. ASID (Address Space Ident.) • Only the low-order 8 bits are implemented. • Each process has it’s own value, and with the 32-bit MMU will create a 40-bit virtual address space. • Extends 4GB addressable space to 1TB

18. continued… • The other registers address how memory is accessed and mapped.See manual pages 26-28

19. Addressing Modes • There is an extensive list of ASM commands that use different addressing modes. • They enable you to do multiple operations and access multiple resources using basic syntax, such as postincrement and predecrement of registers. • Too many to discuss here. See manual pages 37-44.

20. Marketing Overview • 2 Independent decoupled piplelines • 4-stage Instruction Fetch Pipeline (IFP) • 5-stage Operand Execution Pipeline • FIFO I-buffer is the decoupling mechanism • Limited superscalar execution through use of instruction folding • Approaches dual-issue performance but at a much lower silicon cost. • 2-level branch acceleration mechanisms

21. Summary • This processor specializes in small code and quick execution. • Able to extend addressable space well beyond the 4GB virtual memory range • Excels in integer manipulation and DSP functions by use of EMAC module, quite common. • Lots of details in the compressed code, reference guide is a must have.

22. References and Links • ColdFire Family Programmer's Reference Manualhttp://e-www.motorola.com/brdata/PDFDB/docs/CFPRM.pdf • ColdFire V4 General Informationhttp://e-www.motorola.com/collateral/V4PRES.html • Links of Interesthttp://e-www.motorola.com/webapp/sps/site/overview.jsp?nodeId=03M0ylgrpxNM0ynJt6gC