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This document provides a comprehensive overview of the design and manufacturing processes in VLSI technology, particularly focusing on the flowchart and cross-sectional layout of an inverter. Key components such as n-well, polysilicon, n+ and p+ diffusion, and contact methods are discussed. The iterative process of ion implantation and the significance of design rules based on λ are outlined, including a detailed description of DRC (Design Rule Check) procedures to ensure compliance. This guide facilitates understanding the basic ingredients for creating integrated circuits, particularly using the TSMC 0.18 µm process.
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Introduction to Layout Jack Ou, Ph.D. CES 522 V VLSI Design Sonoma State University
S S D D Mask Set
Basic Ingriedents • n-well (N_WELL) • Polysilicon (POLY) • n+ diffusion • p+ diffusion • contact • metal
Manufacturing the n-well • Grow a protective Layer of oxide. • Remove oxide in selected region • Ion Implantation
Poly silicon (doped to make good conductor, Block n+ diffusion) • n-diffusion
p-diffusion, contacts and metal Thick metal oxide provides insulation p+ diffusion is made selectively using silicon dioxide and photo resist
λ • λ is half of the smallest feature size • In 0.18 um, λ is 0.09 um • λ based design rules makes it easy to migrate from one process to process. • Industrial design rules are usually specified in microns, which makes it difficult to migrate to a more advanced process.
Example from tsmc 0.18 um process POLY has a width of 2 λ Contacts are 2 λ x 2 λ
Schematic/Layout of an Inverter VDD p+ diffision n+ diffision Ground
Schematic/Layout of a NAND2 VDD p+ diffision n+ diffision Ground
NWELL+N_Plus_Select+ActiveLayer+Contact to Active Layer+Metal 1
DRC Check: to run DRC First: to see the first DRC violation Next: to step through the DRC errors
DRC Results DRC violation
Repaired Layout Enlarged N Plus Select Reduced Result Count
