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CSE 144 Project Part 2

CSE 144 Project Part 2. Overview. Goal: Implement a placement tool for standard cell design. Multiple rows Routing channel between rows Components of identical height but various width. Problems to be resolved. Assignment of components to rows

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CSE 144 Project Part 2

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  1. CSE 144 ProjectPart 2

  2. Overview Goal: Implement a placement tool for standard cell design • Multiple rows • Routing channel between rows • Components of identical height but various width

  3. Problems to be resolved • Assignment of components to rows • Optimization goal: Reducing inter-row connections • Strategy: Slicing bisection algorithm • Concrete row positions in each row • Optimization goal: Minimizing overall interconnect length in channels • Strategy: Simulated annealing algorithm

  4. Row-based component grouping • Algorithm: slicing bisection for N-row layout • Need to slice (partition) the circuit into N rows • Rows should have similar size • Connection between rows are minimized • Repeatedly partition the circuit Row 1 1 2 5 Example: a 3-row design Row 3 Row 2 7 3 4 6

  5. How to generate slicing? Slicing algorithm requires • unbalanced partitioning • minimized cutsize between rows • Repeatedly apply Fiduccia-Mattheyses algorithm under varying area constraints • Each partitioning step generates one new row

  6. Feed-through problem Partitioning after the 1st step • Components 1&3 fixed in row 1 • Component 2 connected with row 1 • If component 2 assigned to row 3 in the next partition, a feed-through generated Row 1 1 2 5 7 3 4 6 Remaining rows Need to consider the connections between components already assigned and components yet to be assigned

  7. Fixed components Feed-through reduction (1) Step 1 • Partitioning strategy • Always partition the complete set of components • Area constraints change for distinct step • Components already assigned fixed in Partition 1 Row 1 1 1 2 5 7 3 3 4 6 Remaining rows

  8. Feed-through reduction (1) Step 2 • Partitioning strategy • Always partition the complete set of components • Area constraints change for distinct step • Components already assigned fixed in Partition 1 1 1 2 5 7 3 3 4 6 • Components 1 & 3 fixed in Partition 1 • This strategy pushes components heavily connected with 1&3 to be assigned in Partition 1 too

  9. Feed-through reduction (2) • Penalize partitionings generating feed-throughs Partitioning after the 1st step Assign a large penalty value to edges between fixed components and unfixed components 1 2 5 7 3 If 2 is not assigned to Partition 2 in the next partition (the case generating feed-through), cutsize significantly increased 4 6

  10. Intra-row component arrangement • Arrange the components in each row to minimize the overall interconnect cost in the channel • Interconnect cost model: • The overall length of horizontal wires • Ignore consider the feed-through wires 1 4 6 2 3 5 1 4 6 5 2 3

  11. Simulated annealing algorithm • Start from an initial arrangement • Randomly change the position of one component (the position of its neighbors need to be adjusted accordingly) • Accept moves that reduce cost; probabilistically accept moves that increase cost • Try multiple moves at each temperature • Terminate when the benefit is less than 2% in 3 successive temperatures

  12. How to calculate cost? • The horizontal wire length depends on pin positions in components 2 1 3 A 3-pin component • Pin location specification • Pin number increases from left to right • Distance between two adjacent pins is 2 • Each pin is of width 1

  13. How to calculate cost? The cost of the example placement is 32

  14. Summary Inter-row Intra-row Goal: Component arrangement Row generation Algorithm: Slicing bisection Simulated annealing Issues to consider: Feed-through Cost model For the implementation of slicing bisection, we provide to you a set of candidate penalty values {1, 2, 5, 10, 15}, try them and figure out the best one

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