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ECE 456 Computer Architecture

ECE 456 Computer Architecture. Lecture #13 – CPU (II) Instruction Set Design (Cont’d) Instructor: Dr. Honggang Wang Fall 2013. Administrative Issues (Monday, Dec 2). Teaching evaluation Project Final report is due on Dec. 9, Monday. Presentation: Dec. 9 (Monday)

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ECE 456 Computer Architecture

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  1. ECE 456 Computer Architecture Lecture #13 – CPU (II) Instruction Set Design (Cont’d) Instructor: Dr. Honggang Wang Fall 2013

  2. Administrative Issues(Monday, Dec 2) • Teaching evaluation • Project • Final report is due on Dec. 9, Monday. • Presentation: Dec. 9 (Monday) • Exam 2 review on Wednesday Lecture #13

  3. Instructions • Print my last name WANG in the STUDENT NAME box. There is NO need to fill in the corresponding ovals. • Print course and section number45601(for ECE456) in the first 5 positions of the STUDENT ID NUMBER box. There is NO need to fill in the corresponding ovals. • Queries on the Questionnaire are matched to the numbers on the Answer Sheet. E: Strongly Agree; D: Agree; C: Neutral; B: Disagree; A: Strongly Disagree

  4. Review of Lecture #12 In the last lecture, we covered the • Machine instruction characteristics • constituent elements, instruction representation, instruction types, and number of addresses • Instruction set design (1) • types of operands • operation repertoire Lecture #13

  5. Topics • Instruction set design (cont’d) • Addressing modes • How is the operand address specified? • Register • Instruction formats • How are the bits of an instruction organized to define operand addresses and operation of the instruction? Lecture #13

  6. Instruction Set Design Addressing Modes • Immediate • Direct • Indirect • Register • Register indirect • Displacement (Indexed) • Stack Lecture #13

  7. Notations • A: contents of an address field in the instruction • R: contents of an address field in the instruction that refers to a register • EA: actual (effective) address of the location containing the referenced operand • (X): contents of memory location X or register X Lecture #13

  8. Instruction Set Design – Addressing Modes Immediate Addressing • Operand is part of instruction: Operand = A • Example: ADD 5 • Add 5 (operand) to content of the accumulator • Pros & cons • No memory reference is required to fetch data • Fast • Limited range of data Lecture #13

  9. Instruction contains address of operand: EA=A Example: ADD A Add contents of location A in memory to accumulator Pros & cons Single memory reference to access data No additional calculations to work out effective address (EA) Limited address space 2K K = length of address field Instruction Set Design – Addressing Modes Direct Addressing Lecture #13

  10. Memory cell pointed by address field contains the address of (pointer to) the operand: EA = (A) Example: ADD (A) Add contents of cell pointed by contents of A to accumulator Instruction Set Design – Addressing Modes Indirect Addressing (1) Lecture #13

  11. Instruction Set Design – Addressing Modes Indirect Addressing (2) • Pros & cons • Larger address space • 2N where N = a word length > K = length of address field • May be multilevel, cascaded • e.g. EA = (((A))) • An indirection flag bit indicates if EA is contained • Multiple memory accesses to find operand • Hence slower Lecture #13

  12. Operand is held in a register named in the address filed: EA=R Pros & cons Limited number of registers  a small address field needed (3-5 bits) Shorter instructions Faster operand fetch No memory access Fast instruction execution Very limited address space Instruction Set Design – Addressing Modes Register Addressing Lecture #13

  13. Operand is in memory cell pointed by contents of register R: EA = (R) Pros & cons Large address space 2N One less memory access than indirect addressing Instruction Set Design – Addressing Modes Register Indirect Addressing Lecture #13

  14. Implicit register indirect addressing: Stack pointer (SP): contains address of the top of the stack (LIFO, Appendix 10A) EA = top of stack Operands are (implicitly) on top of stack PUSH X: (SP) -1  SP, (X)  (SP) POP X: ((SP))  X, (SP)+1  SP ADD: Pop top two items from stack Add Place result of addition on top of stack Instruction Set Design – Addressing Modes Stack Addressing Lecture #13

  15. Address field holds two values A = base value R = register that holds displacement, maybe implicit or vice versa EA = A + (R) 3 common uses: Relative addressing Base register addressing Indexing Instruction Set Design – Addressing Modes Displacement Addressing (1) Lecture #13

  16. Instruction Set Design – Displacement Addressing (2) Relative Addressing/PC-Relative Addressing • EA = A + (R) • R = Program Counter, being implicit • The address field A (k-bit) • Treated as a twos complement number • A displacement relative to current instruction address indicated by PC • Exploits the principle of locality and cache usage: if most memory references are relatively near to the ins. being executed, then use of this mode can save address bits in Ins. Lecture #13

  17. Instruction Set Design – Displacement Addressing (3) Base-Register Addressing • EA = A + ( R ) • The address field A holds a displacement • Treated as an unsigned integer representation • R contains the base memory address • R may be explicit or implicit • Exploits the principle of locality • Example: • R: segment-base register • Instructions can reference any 1 of 4 areas of 2K words Lecture #13

  18. Instruction Set Design – Displacement Addressing (4) Indexed Addressing (1) • EA = A + ( R ) • The address field A references a base memory address • R contains a displacement from the base • Treated as an unsigned integer representation • R may be explicit or implicit • Good for accessing arrays • Array is stored starting at location A • R=0 • Loop {EA = A + (R), R++} Lecture #13

  19. Instruction Set Design – Displacement Addressing (5) Indexed Addressing (2) • Combinations of indexing and indirect addressing • Postindexing: indexing performed after indirection • EA = (A) + (R) • Contents of A used to point to a direct address • The direct address is then indexed by the value of register R • Preindexing: indexing performed before indirection • EA = (A+(R)) • The location A+(R) contains not the operand but the address of the operand Lecture #13

  20. Instruction Set Design – Addressing Modes Comments • How can control unit determine which addressing mode is being used? • Implicitly specified by OpCode • Using a mode field in instruction • Interpretation of effective address (EA) • Without VM • EA is a main memory address or a register • With VM • EA is a virtual address or a register • Actual mapping to a physical address via paging is transparent to programmers Lecture #13

  21. Hands-On Problems • With the memory depicted below, complete the comments to show what is loaded by each instruction of the program. Note that when the memory is used as a stack, the stack grows from lower address to higher address. X is the symbolic memory address, and X=67. MOVE R1, (X) //indirect addressing: R1  ____ MOVE R2, (R1) //register indirect addressing: R2  ___ MOVE R3, 67 //immediate addressing: R3  ___ PUSH R2 //stack grows to location (__) that contains ___ PUSH R1 //stack grows to location (__) that contains ___ POP R3 //stack shrinks: R3  ___ POP R1 //stack shrinks: R1  ___ MOVE R3, R1 //register addressing: R3  ___ MOVE R2, (R1)-3 //displacement addressing: R2  ___ MOVE R1, ((X)) //2-level indirect addressing: R1  ___ Lecture #13

  22. Agenda • Instruction set design (cont’d) • Addressing modes • How is the operand address specified? • Register • Instruction formats • How are the bits of an instruction organized to define operand addresses and operation of the instruction? Lecture #13

  23. Instruction Formats • Layout of the bits of an instruction in terms of constituent elements, including • OpCode • (implicit or explicit) operand(s) • (implicit or explicit) mechanism indicating addressing mode used for each operand • Usually more than one instruction format in an instruction set Lecture #13

  24. Instruction Formats • Key design issues: • Number of addresses (L12) • Instruction length • Allocation of bits Lecture #13

  25. Instruction Format Design Instruction Length • Affected by and affects: • Memory size, Memory organization, Bus structure (bus width), CPU complexity, and CPU speed • Trade off between powerful instruction repertoire and saving space • More opcodes, more operands, more addressing modes, greater address range  shorter program  longer instruction length  slower instruction fetch Lecture #13

  26. Instruction Format Design Instruction Length (Cont’d) • Should be a multiple of the character length (8-bit) and fixed-point number length (a word length) Lecture #13

  27. Summary of Lecture #13 • Addressing modes • How is the operand address specified? • Immediate, Direct, Indirect, Register, Register indirect, Displacement (relative, base-register, indexing), stack • Instruction formats • How are the bits of an instruction organized to define operand addresses and operation of the instruction? • Number of addresses, instruction length (fixed/variable), allocation of bits (fixed/variable OpCode length) Lecture #13

  28. Things To Do • Read Ch 11.2 for example addressing modes • Read Ch 11.4 for instruction formats • Check out the class website about lecture notes Lecture #13

  29. Hands-On Problems (Extra Credits) • With the memory depicted below, indicate what values the following instructions load into the registers? • MOVE R, 30 //immediate addressing: R  ________ • MOVE R, (X) //indirect addressing: R  _______ • MOVE R1, R //register addressing: R1  _______ • MOVE R1, (R) //register indirect addressing: R1  _______ • MOVE R1, (R) +1 //displacement addressing: R1  _______ • MOVE R1, X //direct addressing: R1  ______ Lecture #13

  30. Instruction Format Design Instruction Format Examples • PDP-8 • PDP-10 • PDP-11 • VAX • Pentium • PowerPC Ch 11.3 Ch 11.4 Lecture #13

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