ECE 456 Computer Architecture

1. ECE 456 Computer Architecture Lecture # – Exam#1 Review Instructor: Honggang Wang Fall 2013

2. Administrative Issues(Wednesday, 10/16/2013) • Exam #1 2:00pm ~ 3:15pm, Monday, Oct 21 • Project Proposal due Oct 28, 2013 • This lecture • Exam #1 review • Exam #1 sample questions • Homework #1 solution discussion

3. Review of Lecture #1 - #4 • Overview of Computer Systems • The Memory System

4. Part I: Computer System Overview • Computer generations and evolution (L#1) • The evolution of computers has been characterized by increasing processor speed, memory capacity, I/O capacity & speed; and decreasing component size

5. Part I Review (Cont’d) • Performance balancing is a critical issue in computer system design (L#1) • Cache memory (L#6) • Enhancements to DRAM main memory (L#5) • RAID (L#7)

6. Part I Review (Cont’d, L#2) • Computer architecture • coined by IBM System/360 group in 1964 • the structure of a computer that a machine language programmer must understand to write a correct program for a machine • Computer organization • the operational units and their interconnections that realize the architectural specifications • how the architectural features are implemented • A particular architecture can span many years and encompass a number of different computer models

7. Part I Review (Cont’d, L#2) • Contemporary computer architecture: • von Neumann architecture • memory with addressable locations • data and instructions are stored in a single read-write memory • basic sequential execution (unless explicitly modified) • interrupts and multiple interrupts • why interrupt? transfer of control • sequential and nested multiple interrupt processing

8. Part I Review (Cont’d, L#3) • Concept of computer function & structure • Structure is the way in which the components are interrelated • Function is the operation of each individual component as part of the structure • Function: • computer view: 4 basic functions • program view: instruction cycle • Structure: • hierarchical system structure • bus interconnection structures: design elements (bus width)

9. Part I Review (Cont’d, Extra Notes) • Basic number systems concepts (base, positional/place value, symbol value) • Binary, octal, decimal, and hexadecimal number systems • Number systems conversions • Decimal  binary/octal/hex • Binary  octal/hexadecimal

10. Binary Octal/hex • To convert from binary to hex (octal), simply divide the binary number into 4-bit (3-bit) group (from right to left) and then write those groups over the corresponding digits of the hex (octal) number • To convert from hex (octal) to binary, simply write each hex (octal) digit its 4-digit (3-digit) binary equivalent

11. Review of Lecture #1 - #8 • Overview of Computer Systems • The Memory System

12. Memory Lectures Memory Hierarchy (L#4)* Performance Imbalance * Principle of Locality * Error correction (SEC) L#6 L#5 L#8 (Ignore) L#7 C A C H E CPU MAIN MEMORY VIRTUAL MEMORY I/O STORAGE DEVICES Registers External Memory Internal Memory OS level Not real

13. Part II Review (Cont’d, L#4) • Characteristics of memory systems • location: external and internal • capacity: in term of byte or word • transfer unit: governed by data bus length or a block • access methods: sequential, direct, random, & associative • performance: latency, memory cycle time, & transfer rate • physical types: magnetic, optical, semiconductor, etc • physical characteristics: volatile, erasable

14. Part II Review (Cont’d, L#4) • Trade-off among capacity, speed, and cost • Dilemma: users always want UNLIMITED amounts of FAST memory with low cost • Memory hierarchy is the solution • goal: to provide a memory system with speed almost as fast as the fastest level and cost almost as low as the cheapest level • basis of success: principle of locality • how? (3 diagrams)

15. Part II Review (Cont’d, L#4) • Error correction in memory • error types: soft error & hard failures • error correction logic • hamming distance & code distance • single-bit and multiple-bit parity codes • single error correcting (SEC) code (4 steps)

16. A Computer System (L1) Computer architecture =von Neumann architecture + interrupts (L2) Central Processing Unit > = L12 Interconnection Bus Memory Input /Output L10, L11 L4 ~ L8 L3

17. Exam#1 • Time: Monday, October 21, 2:00 ~ 1:15pm • Place: Group II – 212 • Requirements: • Arrive on time! • Random seat will be assigned. • Open-book open-notes in-class exam • No sharing notes during the exam • Individual work

18. Prepare for Exam #1 • Review lecture notes #1 ~ #4 • Review homework #1 • Review all the review questions and hands-on problems discussed in the class • Ask questions if there are

19. Questions? • Dr. Wang (Instructor) • Email:   hwang1@umassd.edu • Office:  II-209B

20. Good Luck!

21. Exercise (2) • Convert the following numbers to their decimal equivalents 10011012 1101.112 1AB.616 173.258

22. 26 bytes (x) 217 bytes (x) 1024 bytes (x) 216 bytes (x) 1E7 bytes (x) 210 bytes (x) 232 bytes (x) No answer (x) 1 Mega bytes = 2?bytes From Background Survey

23. Solution (4) • Do you know the equivalent hexadecimal,octal, and decimal values of the binary number 11001010? ______Yes _______No If you answered Yes, please indicate them below: • Equivalent hexadecimal number:__CA___________ • Equivalent octal number: _______312___________ • Equivalent decimal number: _____202_____________ • What is the equivalent binary number of the decimal number 63? ________111111_____________ From Background Survey

24. Nested Interrupt Processing (2): Example • A system has three I/O devices • a printer with priority 2 • a disk with priority 4 • a communication line with priority 5 • Multiple interrupts (each takes 10 time units) Increasing priority time 0 10 15 20 25 communication line interrupt printer interrupt disk interrupt

25. Time Sequence of Example Multiple Interrupts time 0 10 15 20 25 disk Interrupt (4) printer Interrupt (2) comm. line Interrupt (5) 2 1 3 4 6 5

26. Computer Program Execution Function Example (1) 0 1 15 • Both data & instructions are stored in a 16-bit memory • Integer • Instruction • CPU registers: PC, IR, AC, MBR, MAR • Operation codes • 0001: load AC from memory • 0010: store AC to memory • 0101: add to AC from memory S 0 4 3 15 Opcode Address

27. Computer Program Execution Function Example (2) fetch execution M(940) + M(941) M(941)

28. Step 1: The PC contains 300, the address of the first instruction. This value is loaded in to the MAR. The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be done in parallel. The value in the MBR is loaded into the IR. How does the operation process look like if MAR and MBR are used?

29. Steps 2 - 6 • Step 2: • The address portion of the IR (940) is loaded into the MAR. • The value in location 940 is loaded into the MBR. • The value in the MBR is loaded into the AC. • Step 3 – Step 6???

30. L#2&3 Review Questions (True/False) • _____ Computer architecture is concerned with the hardware details that are transparent to the machine language programmer • _____ Different models in the same computer family may have different organizations, but share the same architecture • _____ In nested interrupt processing method, the interrupt will be disabled before the CPU transfers the control to the interrupt service routine • _____ Consider a system with two I/O devices: a printer and a disk with increasing priorities of 2 and 3, respectively. A user program begins at t=0. At t=5, a disk interrupt occurs; at t=13, a printer interrupt occurs. Each interrupt processing time is 10 time units. Then the printer interrupt handling will be completed at t=25 if using Sequential method; and at t=23 if using Nested method. • ______ The octal equivalent of hexadecimal number C2A is 1452 • ______ Typically the data bus width determines the memory capacity of a computer system

31. How the goal can be achieved? Example • 2-level memory hierarchy • Level 1: size (S1), cost/bit (C1), access time (T1) • Level 2: size (S2), cost/bit (C2), access time (T2) • H (hit ratio): fraction of accesses involving only faster Level 1 • Assumption: • Processor access Level 1 directly • Ignoring decision making time • For system: Ts, Cs ?

32. Review Questions (10 extra points) • Consider a memory system containing a cache and a main memory. The cache contains 32Kbytes and has an access time of 30ns. The average cost per bit of the cache memory is $10-4. The main memory contains 512Mbytes and has an access time of 0.1s. The average cost per bit of the main memory is $10-5. If a referenced word is in the cache (cache hit), then the CPU can access it directly. If it is in the main memory but not in the cache, the word is first transferred to cache and then accessed by the CPU. • What is the average cost per bit for the entire memory system? • If the average access time to the memory system is 20% greater than the cache access time, what is the cache hit ratio?

33. Single-Bit Parity Codes (1) • Odd Parity: the total number of 1s in the code word is odd • 0010  • Even Parity: the total number of 1s in the code word is even • 0010  0010 0 0010 1

34. SEC Codes (4): How to generate check bits? • Number all bit positions from 1 to (M+K) • Arrangement of bit positions • Check bits: bit positions whose position numbers are power of 2 • Data bits: other positions

35. SEC Codes (4): How to generate check bits? • Check-bit generating rule: • Each check bit is generated by performing exclusive-or operation on every data bit whose position number contains a 1 in the same bit as the position number of that check bit