Download Presentation
## Chapter 4: Combinational Logic

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -

**Chapter 4:Combinational Logic**Dr Mohamed Menacer Taibah University 2007-2008**4-1 Multiplexer**Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX input is selected from {0, 1, C, C} to pick the desired behavior of the minterm pair.**Multiplexer Function**• Multiplexer Y = A • S + B • S´ OR AND NOT**Truth Table**x y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Half-Adder Logic Equations C = x • y S = x y Schematic**Truth Table**x y z C S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Full-Adder Logic Equations C = x’yz + xy’z + xyz’ + xyz = z • (x’y+xy’) + xy • (z+z’) = z • (x y) + x • y = MAJ (x,y,z) S = x’y’z + x’yz’ + xy’z’ + xyz = x’yz’ + xy’z’ + x’y’z + xyz = z’(x’y + xy’) + z(x’y’ + xy) = z’(x y) + z(x y)’ = (x y) z = x y z**Adding Two Numbers**• Many Types of Adders: Some examples: • Bit Serial Adder • Add time = n x f • Cascade Stages • Ripple carry adder • Add time = n x tPD • Carry Look Ahead Adder • Generate carries in parallel • e.g., 4-bit AM2902. Can have “look ahead” of the “look ahead” units.**Negative Numbers and Subtraction**• Several different codes for negative numbers • 2's complement • 1's complement • signed magnitude • others • For 2's complement, subtraction is implemented with the same hardware by negating the subtrahend. This is done by inverting each bit and adding one. The one can be added by setting the carry-in to the first stage equal to 1, saving an operation.**Decoder Fundamentals**• Route data to one specific output line. • Selection of devices, resources • Code conversions. • Arbitrary switching functions • implements the AND plane**1 1**1 0 0 1 00 Decoder What happens when the inputs goes from 01 to 10?**Why Encode?A Logarithmic Relationship**Lets say we have N inputs to a decoder, the number of outputs will be equal to 2^N**Decoder with Enable**Demultiplexer Decoder with Enable**Encoder**• An encoder translates a set of inputs into a binary encoding, • Can be thought of as the converse of a decoder. • A priority encoder imposes an order on the inputs.**Sequential Logic**• The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. • There is a need for circuits with a memory, which behave differently depending upon their previous state. • Sequential circuits use current input variables and previous input variables by storing the information and putting back into the circuit on the next clock (activation) cycle.**The Clock Paces the System**In a positive logic system, the “action”happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.**Negative Pulse**Positive Pulse Positive Edge Negative Edge Negative Edge Positive Edge Clock Pulse Definition Edges can also be referred to as leading and trailing.**A NOR Gate with a Lumped Delay**This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop.**Flip-Flops**Flip-flops are the first stage in sequential logic design which incorporates memory (storage of previous states).**Types of Flip-Flops**• SR type Flip-flop or Set / Reset • D type Flip-flop or Data / Delay • JK type Flip-flop • T type Flip-flop or Triggered /Toggle**The S-R (Set-Reset) Flip-Flop**The operation of an SR flip-flop is as follows: The Set input will make Q goto 1 The Reset input will make the output Q goto 0 i.e. reset the output.Both Set and Reset at logic 1 is not allowed as this is not a logical pair of inputs. The S-R flip-flop is an active high (positive logic) device.**A Clocked S-R Flip-Flop**The clock signal, CLK, turns on the inputs to the flip-flop.**The Clocked D (Data) Flip-Flop**The operation of the D type flip-flop is as follows: Any input appearing (present state) at the input D, will be produced at the output Q in time T+1 (next state). The operation of the D type delays any input by exactly one clock cycle. Cascading several D type flip-flops together can produce delaying circuits The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop solves this problem:**8 Bits D (Data) Flip-Flop**One D type flip-flop can store one bit of information for one clock cycle. To have eight bits of information, simply arrange eight flip-flops in parallel with a common clock.**The Master-Slave Flip-Flop**The rising edge of the clock clocks new data into the Master, while the slave holds previous data. The falling edge clocks the new Master data into the Slave.**Decoder**(AND plane) MagneticCoreMemory Register**Semiconductor Memory**Decoder (AND plane) OR plane**UT4090 RAM Module**• Dual-port • 1152 bits per cell • Four configurations • 64 X 18 • 128 X 9 • 256 X 4 • 512 X 2 RE WA(8:0) WD(17:0) RCLK RA(8:0) WE WCLK RD(17:0) ASYNCRD MODE(1:0)