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Chapter 6

Chapter 6. Combinational – Circuit Building Blocks. Chapter Objectives. In this chapter you will learn about: Commonly used combinational subcircuits Multiplexers, which can be used for selection of signals and for implementation of general logic functions

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Chapter 6

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  1. Chapter 6 Combinational – Circuit Building Blocks

  2. Chapter Objectives • In this chapter you will learn about: • Commonly used combinational subcircuits • Multiplexers, which can be used for selection of signals and for implementation of general logic functions • Circuits used for encoding, decoding, and code-conversion purposes • Key VHDL constructs used to define combinational circuits

  3. s f s w w 0 0 0 0 f w 1 w 1 1 1 (b) Functional table (a) Graphical symbol A 2-to-1 Multiplexer w 0 s f w 1 (c) Sum-of-products circuit

  4. s 0 w 0 s 1 w 1 f w 2 w 3 (c) Circuit A 4-to-1 Multiplexer s 0 s 1 w 00 0 w 01 1 f w 10 2 w 11 3 (a) Graphic symbol s s f 1 0 w 0 0 0 w 0 1 1 w 1 0 2 w 1 1 3 (b) Functional table F = s1’ s0’ w0+ s1’ s0 w1 + s1 s0’ w2 + s1 s0 w3

  5. Using 2-to-1 Multiplexers to Build a 4-to-1 Multiplexer s 1 s 0 w 0 0 w 1 1 0 f 1 w 0 2 w 1 3

  6. A 16-to-1 Multiplexer

  7. A Practical Application of Multiplexers x s 0 1 y 1 1 s x y 1 1 x y 2 2 x 0 2 y 2 1 (a) A 2x2 crossbar switch (b) Implementation using multiplexers

  8. Synthesis of a Logic Function Using Multiplexers w w f 1 2 f w 1 0 0 0 w 0 2 1 0 1 w w 1 w w f 2 2 1 2 1 w 1 0 1 0 1 1 0 0 0 0 1 0 1 1 f 1 1 0 1 (b) Modified Table, a Functional table 0 0 1 1 w 1 (a) Implementation using a 4-to-1 multiplexer w 2 f (c) Circuit

  9. w w w f Implementation of the Three-Input Majority Function Using a 4-to-1 Multiplexer 1 2 3 w w f 1 2 0 0 0 0 0 0 0 0 0 1 0 w 0 1 3 0 1 0 0 w 1 0 3 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 w 2 w 1 0 w 3 f 1 (a) Truth table (b) Modified Functional table (c) Circuit

  10. Three-Input XOR Implemented with 2-to-1 Multiplexers w w w f 1 2 3 0 0 0 0 0 0 1 1 w Å w w 2 2 3 w 0 1 0 1 1 w 0 1 1 0 3 1 0 0 1 f 1 0 1 0 Å w w 2 3 1 1 0 0 1 1 1 1 XOR implementation using Fig 6.7. (a) Truth table (b) Circuit

  11. Three-Input XOR Function Implemented with a 4-to-1 Multiplexer w w w f 1 2 3 0 0 0 0 w 3 w 0 0 1 1 2 w 1 0 1 0 1 w 3 w 0 1 1 0 3 1 0 0 1 f w 3 1 0 1 0 1 1 0 0 w 3 1 1 1 1 (b) Circuit (a)Truth table

  12. The Three-Input Majority Function Implemented Using a 2-to-1 Multiplexer w w w f 1 2 3 f 0 0 0 0 w 1 0 0 1 0 w w 0 2 3 0 1 0 0 w + w 1 2 3 0 1 1 1 1 0 0 0 w 1 w 1 0 1 1 2 w 1 1 0 1 3 f 1 1 1 1 (a) Truth table (b) Circuit

  13. Comparison of Three-Input XOR Implementations using 2-to-1 and 4-to-1 Multiplexers w 2 w 1 w 2 w w 3 1 f w 3 XOR implementation using Fig 6.7. f (a) Circuit (b) Circuit

  14. Truth Tables for Comparison of Three-Input XOR Implementations using 2-to-1 and 4-to-1 Multiplexers w w w f 1 2 3 w w w f 0 0 0 0 1 2 3 0 0 1 1 Å w w 0 0 0 0 2 3 w 0 1 0 1 3 0 0 1 1 0 1 1 0 0 1 0 1 1 0 0 1 w 3 0 1 1 0 1 0 1 0 Å w w 2 3 1 0 0 1 1 1 0 0 w 3 1 0 1 0 1 1 1 1 1 1 0 0 w 3 1 1 1 1 (a) Functional table (b) Functional table

  15. Implement the function f = w1 w2+ w1w3 + w2 w3 using only: 4-to-1 Multiplexers 2-to-1 Multiplexers An Example

  16. w w w f 4-to-1 Multiplexer Implementation 1 2 3 w w f 1 2 0 0 0 0 0 0 0 0 0 1 0 w 0 1 3 0 1 0 0 w 1 0 3 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 w 2 w 1 0 w (b) Modified Functional table 3 f 1 (a) Truth table (c) Circuit

  17. 2-to-1 Multiplexer Implementation w w 2 1 Hint: Expand 4-to-1 Multiplexers Using 2-to-1 Multiplexers 0 w 3 f 1 (d) Circuit

  18. An n-to-2n Binary Decoder w y 0 0 n n 2 inputs w outputs n – 1 y n Enable 2 – 1 En

  19. A 2-to-4 Decoder w w y y y y En 1 0 0 1 2 3 0 0 0 1 0 0 1 w 0 0 1 0 1 0 0 1 y 1 1 0 0 0 1 0 0 w 1 1 1 0 0 0 1 1 x x 0 0 0 0 0 y 1 (a) Truth table y 2 w y 0 0 w y 1 1 y y 3 2 y En 3 En (c) Logic circuit (b) Graphical symbol

  20. A 3-to-8 Decoder Using Two 2-to-4 Decoders w y w y 0 0 0 0 w y w y 1 1 1 1 y y 2 2 w y 2 y En 3 3 y w y En 4 0 0 y w y 5 1 1 y y 6 2 y y En 7 3

  21. A 4-to-16 Decoder Built Using a Decoder Tree

  22. A 4-to-1 Multiplexer Built Using a Decoder w 0 w 1 s w y 0 0 0 s w y f 1 1 1 y w 2 2 y En 1 3 w 3

  23. A 2n-to-n Binary Encoder w outputs 0 y 0 n n 2 inputs y n – 1 w n 2 – 1

  24. A 4-to-2 Binary Encoder w 0 w w w w y y 3 2 1 0 1 0 w 1 y 0 0 0 1 0 0 0 0 0 1 0 0 1 w 2 0 1 0 0 1 0 1 0 0 1 1 0 y 1 w 3 (a) Truth table (b) Circuit

  25. Truth Table for a 4-to-2 Priority Encoder w w w w y y z 3 2 1 0 1 0 0 0 0 0 d d 0 0 0 0 1 0 0 1 x 0 0 1 0 1 1 x x 0 1 1 0 1 x x x 1 1 1 1

  26. A BCD-to-7 Segment Display Code Converter a b w 0 c w c e g w w w w a b d f 1 3 2 1 0 d w 2 e 0 0 0 0 1 1 1 1 1 1 0 w 3 f 0 0 0 1 0 1 1 0 0 0 0 g 0 0 1 0 1 1 0 1 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 (a) Code converter 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 a 1 1 1 0 1 1 1 0 0 0 0 f b 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 0 1 1 g e c (c) Truth table d (b) 7-segment display

  27. A Four-Bit Comparator Circuit

  28. Truth Table for an 8-to-3 Binary Encoder

  29. Circuit for Example 6.27

  30. Binary to Gray Code Conversion

  31. VHDL Code for a 2-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; END Behavior ;

  32. VHDL Code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ;

  33. VHDL Code for a 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE mux4to1_package IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; END mux4to1_package ;

  34. Hierarchical Code for a 16-to-1 Multiplexer 1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 2 LIBRARY work ; 4 USE work.mux4to1_package.all ; 5 ENTITY mux16to1 IS 6 PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; 7 s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; 8 f : OUT STD_LOGIC ) ; 9 END mux16to1 ; 10 ARCHITECTURE Structure OF mux16to1 IS 11 SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; 12 BEGIN 13 Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; 14 Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; 15 Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; 16 Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; 17 Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; 18 END Structure ;

  35. VHDL Code for a 2-to-4 Binary Decoder

  36. Specification of a 2-to-1 Multiplexer Using a Conditional Signal Assignment LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ;

  37. VHDL Code for a Priority Encoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END priority ; ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;

  38. Less Efficient Code for a Priority Encoder

  39. VHDL Code for a Four-Bit Comparator LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

  40. VHDL Code for a Four-Bit Comparator for Signed Numbers LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY compare IS PORT ( A, B : IN SIGNED(3 DOWNTO 0) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE Behavior OF compare IS BEGIN AeqB <= '1' WHEN A = B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ; END Behavior ;

  41. Code for a 16-to-1 Multiplexer Using a Generate Statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.mux4to1_package.all ; ENTITY mux16to1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux16to1 ; ARCHITECTURE Structure OF mux16to1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Muxes: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

  42. Hierarchical Code for a 4-to-16 Binary Encoder

  43. A 2-to-1 Multiplexer Specified Using an If-Then-Else Statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ; END PROCESS ; END Behavior ;

  44. Alternative Code for a 2-to-1 Multiplexer Using an If-Then-Else Statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE Behavior OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END Behavior ;

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