STM32VL- Training

1. STM32VL- Training Esprit 2012 V1.0

2. CONTENTS • PART I : CORTEX-M3 • PART II : STM32F100 device • PART III : STM32 Value line Discovery Kit

3. PART - I CORTEX M3

4. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

5. OBJECTIVES • Familiarize with Cortex M3 • At the end of the part you will be able to List the main features of the Cortex M3

6. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

7. What is ARM(Advanced Risc Machines)? • ARM is an UK company that designs innovative 32-bit microprocessors • ARM leads the world of RISC microprocessor cores • ARM develops directly and through partnership the tools, systems and services to support its architecture.

8. Why use an ARM-based processor? • Most popular 32-bit core • Becoming an industrial standard like the C51 • Compatible leading edge core roadmap • ARM7 -> ARM9 /10->CortexM3, M4,… • Large number of product choices • Multiple vendors means a large choice

9. Why use an ARM-based processor? Sales in billions of dollars

10. Why Cortex M3?

11. Why Cortex M3? More Than 28 company ST, NXP, Atmel, Samsung… Cortex-A Series, applications processors for complex OS and user applications. Cortex-R Series, real-time systems profile. Cortex-M Series, microcontroller profile optimized for cost-sensitive applications.. The number at the end of the Cortex name refers to the relative performance level, with 1 the lowest and 8 the highest.

12. ARM Cortex-M code size advantage explained

13. Industry standard

14. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

15. Cortex-M3 Processor(1/2) • Hierarchical processor integrating core and advanced system peripherals • Cortex-M3 Processor • Cortex-M3 core • Configurable interrupt controller • Bus matrix • Advanced debug components(ETM…) • Optional MPU(Not available in STM32F10x) • Cortex-M3 core • Harvard architecture • 3-stage pipeline prediction • Thumb®-2 • ALU w. H/W divide and single cycle multiply

16. Cortex-M3 Processor(2/2) Non Maskable Interrupt 3-Stage Pipeline, Harvard Architecture, Thumb-2 ISA (or Thumb) 30K* Gates 1-240 Configurable Interrupts with Configurable Priority Levels SWD or JTAG Breakpoints Data Watchpoints & Trace * Preliminary gate counts & power consumption based on initial implementation Gate Counts are based on TSMC 0.18 at 50MHz Optional ETM & MPU gate counts not included Cortex M3 Total 60k* Gates

17. Cortex-M3 Processor Main Features • ARM v7M Architecture • Thumb-2 Instruction Set Architecture • Mix of 16 and 32 bit instructions for very high code density • Harvard architecture • Separate I & D buses allow parallel instruction fetching & data storage • Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is addresses. • Integrated Bus Matrix • Data memory management • 3 Stage Pipeline • Integrated System Timer (SysTick) for Real Time OS

18. Data Memory management (1/7) • Cortex-M3 includes two technologies to reduce Data memory requirements: • Unaligned Data Support • Atomic Bit Banding • These technologies can dramatically improve data (SRAM) memory utilization, potentially enabling silicon designers and users to reduce the amount of SRAM required and dramatically impacting silicon usage.

19. Reduces SRAM Memory Requirements By Over 50% Less Memory - LowER Cost devices Data Memory management(2/7) • Unaligned Data Support: Other Core does not support unaligned data ARM Cortex-M3 supports unaligned data that can improve SRAM utilization Long (32) Long (32) Long (32) Long (32) short (16) short (16) short (16) Char Char Char Char short (16) Char Data aligned on word boundaries Char Char Char Free space Can be used Unused (wasted) space

20. long (32) long (32) char (8) char (8) long (32) … long (32) … long char (8) char (8) char (8) char (8) char (8) char (8) int (16) long (32) … … long int (16)c int (16) long (32) char (8) int (16) long … int (16)c char (8) … long (32) int (16) long (32) Reduces SRAM Memory Requirements By Over 25% Data Memory management(3/7) Structure management example 32bit machinewhich doesnot supportunaligned data Dataaligned Free space for the rest of the application Unused (wasted) space

21. Traditional method Disable external events 32bit REALmemory image Read byte (RAM, register) @Rbase+N b31 b0 0 1 0 0 1 0 1 1 example: 20000000h to 200FFFFFh Mask and modify bit element b31 VIRTUAL aliased bit banding image X X X X X 1 X X Write byte (RAM, register) 0 1 0 0 1 1 1 1 b0 Enable external events Data Memory management(4/7) • Bit Banding: • Speed and code size optimized Cortex-M3 implementation ♦ Bit Banding done by bus matrix. ♦ Single instruction Read/Modify/Write (no more masking). ♦ No new instruction set  Use standard data one (AND, OR, XOR…). Optimized RAM, peripherals and IOs registers accesses Easy multi-task semaphore management

22. Data Memory management(5/7) 32MB alias region 1MB Peripheral bit-band region

23. Data Memory management(6/7) • Bit Banding formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr:is the address of the word in the alias memory region that maps to the targeted bit. bit_band_baseis the starting address of the alias region (0x22000000 ) byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position of the targeted bit(0-7) . Example -1: How to map bit 2 of the byte located at Peripheral X address 0x20000300 in the alias region (Peripheral X based address is 0x20000000):

24. Data Memory management(7/7) • Solution: 0x22006008 = 0x22000000 + (0x300*32) + (2*4). Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference Manual.

25. Instruction Pipeline(1/3) • PC points to fetch stage: Instruction fetched from memory Instruction decoded Register(s) read from Register Bank Shift and ALU operation or memory access Write register(s) back to Register Bank

26. Instruction Pipeline(2/3) • Optimal Pipelining: • All operations here are registers (single cycle execution) • In this example it takes 6 cycles to execute 6 instructions • Clock cycles per Instructions (CPI) = 1

27. 1 2 3 4 5 6 7 8 9 F D E F D F F D E F D E F D E Instruction Pipeline(3/3) • Flushing : A flush of the pipeline can occur because of • A Branch • An exception • A breakpoint • Branch Pipeline Example: Cycle Address Operation 0x8000 B 0x8FEC 0x8002 SUB 0x8004 ORR 0x8FEC AND 0x8FEE ORR 0x8FF0 EOR F- Fetch D - Decode E - Execute

28. Registers R0-R12 are simple registers that can be used to hold program variables. Registers R13-R15 have special functions within the Cortex CPU. R13: Register R13 is used as the stack pointer R14: called the link register. used to store the return address when a call is made to a procedure R15: is the program counter xPSR:The Program Status Register contains status fields for instruction execution Register Set(1/2) Register Set R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13(SP) R14(LR) R15 (PC) xPSR

29. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • System Timer (SysTick) • Debug Capabilities

30. Interrupt Handling • The Cortex-M3 processor integrates an advanced Nested Vectored Interrupt Controller (NVIC) • The NVIC supports up to 240 dynamically reprioritizes interrupts each with up to 256 levels of priority • Supports advanced features for next generation real-time applications: • Tail-chaining of pending interrupts • Interrupt Pre-emption • Late Arrival

31. 12 Interrupt Response- Tail Chaining(1/3) IRQ1 Highest IRQ2 42 CYCLES PUSH ISR 1 POP PUSH ISR 2 POP ARM7 Interrupt handling in assembler code 16 26 26 16 Tail-chaining PUSH ISR 1 ISR 2 POP Cortex-M3 Interrupt handling in HW 65% Saving in Clock Cycles 12 6 6 CYCLES • ARM7 • 26 cycles from IRQ1 to ISR1 entered • Up to 42 cycles • 42 cycles from ISR1 exit to ISR2 entry • 16 cycles to return from ISR2 • Cortex-M3 • 12 cycles from IRQ1 to ISR1 entered • 12 cycles • 6 cycles from ISR1 exit to ISR2 entry • 12 cycles to return from ISR2

32. 12 Interrupt Response – Preemption(2/3) IRQ1 Highest IRQ2 42 CYCLES ISR 1 POP PUSH 2 ISR 2 POP ARM7 16 26 16 POP ISR 1 POP ISR 2 Cortex-M3 1- 12 6 7-18 CYCLES

33. 26 16 16 26 12 6 Interrupt Response – Late Arriving(3/3) Less than 12 cycle IRQ1 Highest IRQ2 PUSH PUSH ISR 1 POP POP ISR 2 ARM7 ISR 2 POP PUSH ISR 1 Cortex-M3 Tail-Chaining

34. Interrupt Response – Lab More than12 cycle Highest NMI IRQ1 IRQ2 IRQ3 Less than12 cycle PUSH PUSH NMI ISR 1 POP ISR 2 ISR 3 POP ISR 2 Starts • Push for ISR1 begins • Pre-empted by NMI • New instruction fetch in parallel minimises time to NMI • Cortex-M3 • Following NMI processor tail-chains into ISR1 • ISR2 Completed • Pop only occurs on return to “Main”

35. NVIC Registers • Each interrupt input has several registers to control it • Enable/Disable Bit • Enable or disable the interrupt • Can be set, cleared or read • Pending Bit • If the pending bit is set, then the interrupt is pending • A pending interrupt can only be taken (become active) if it is enabled and it has sufficient priority to run • Pending bit can be set, cleared or read • Active Bit • A bit is set if the interrupt is executing or “active-stacked” • “Active-stacked” means the interrupt was executing, but was pre-empted by another higher-priority interrupt • Active register is normally read only • Priority field • priority management for each interrupt

36. Cortex-M3 Exception Types

37. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

38. Cortex-M3 Memory Map

39. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

40. Power Management • 8bit Microcontroller like power mode management • SLEEP NOW ♦ “Wait for Interrupt” instructions to enter low power mode • No more dedicated control register settings sequence ♦ “Wait for Event” instructions to enter low power mode • No need of Interrupt to wake-up from sleep • Rapid resume from sleep • SLEEP on EXIT ♦ Sleep request done in interrupt routine ♦ Low power mode entered on interrupt return • Very fast wakeup time • DEEP SLEEP ♦ Long duration sleep • From product side: PLL can be stopped or shuts down the power to digital parts of the system • Enables low power consumption • Optimized RUN mode CORE power consumption

41. CONTENTS • Objectives • Introduction • Cortex-M3 Processor • Cortex M3 interrupt handling • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

42. System Timer (SysTick) • Flexible system timer • 24-bit self-reloading down counter with end of count interrupt generation • 2 configurable Clock sources • Suitable for Real Time OS or other scheduled tasks In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8 (provided externally by the Reset Clock Control )

43. CONTENTS • Objectives • Introduction • What is ARM ? • Why use an ARM-based processor? • Cortex-M3 Processor • Cortex-M3 Processor Main Features • Data Memory • Instruction Pipeline • Write Buffer • Privilege, Modes, Stacks and Register Set • Cortex M3 interrupt handling • Exception/Interrupt Handling, • NVIC Registers • Cortex-M3 Exception Types • Vector Table • Cortex-M3 Memory Map • Power Management • System Timer (SysTick) • Debug Capabilities

44. SWD Debug Capabilities • Three solutions are possible : More pins available for the application ETM JTAG • Joint Test Action Groupeasy flashed application debugging ♦ 8 hardware breakpoints • Serial Wire Debug for targeted low bandwidth data trace • Enhanced Thematic Mapper capability for better real time debugging • ♦ Instruction trace only

45. Performance Real time 5 reasonsto chooseCortex-M3 PowerManagement OptimizedMemory PowerfulDebugging

46. PART - II STM32F10x Device

47. CONTENTS • Objectives • STM32F10x Device • Block Diagram • Memory mapping and boot modes • System Architecture • STM32F10x System Peripherals • Main features • STM32F10x Minimum External Components • STM32F10x standard peripheral Library • What is CMSIS? • Package organization • STM32F10xxx standard peripheral library architecture • Coding conventions • Using the Library

48. OBJECTIVES • Familiarize with STM32F10x device • At the end of the training you will be able to • List the main features of the STM32F10x system peripherals • Configure the standard library environment • Develop your applications using the STM32F10x standard library

49. CONTENTS • Objectives • STM32F10x Device • Block Diagram • Memory mapping and boot modes • System Architecture • STM32F10x System Peripherals • Main features • STM32F10x Minimum External Components • STM32F10x standard peripheral Library • What is CMSIS? • Package organization • STM32F10xxx standard peripheral library architecture • Coding conventions • Using the Library

50. More choice with STM32 series • The general purpose F‑1 series addresses a wide range of applications, from the lowest price‑sensitive design to the computing intensive, high memory Footprint • Get the highest performance with the F‑2 series for computing intensive application and advanced connectivity. The F‑2 series maintains the compatibility with the F‑1 series. • Get the highest performance with the Design ultra‑low‑power applications with the L‑1 series for those who are power conscious and seek the absolute lowest energy consumption. The L‑1 series maintains the compatibility with the F‑1 series.