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Interconnect and Packaging Lecture 2: Scalability

Interconnect and Packaging Lecture 2: Scalability. Chung-Kuan Cheng UC San Diego. Outlines. Trends of Interconnect and Packaging Scalability References. I. Trends of High Performance Interconnect and Packaging. I. Trends. On-Chip Interconnect Delay (5-40 times of Speed of Light 5ps/mm)

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Interconnect and Packaging Lecture 2: Scalability

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  1. Interconnect and PackagingLecture 2: Scalability Chung-Kuan Cheng UC San Diego

  2. Outlines • Trends of Interconnect and Packaging • Scalability References

  3. I. Trends of High Performance Interconnect and Packaging

  4. I. Trends • On-Chip Interconnect • Delay (5-40 times of Speed of Light 5ps/mm) • Power Density (> ½) • Clock Skew: Variations (5GHz) • Off-Chip Interconnect and Packaging • Number of pins (limited growth) • Wire density (scalability) • Speed and distance of interconnect

  5. I. Trends • On-chip Global Interconnect trend • Concerns: Speed, Power, Cost, Reliability

  6. I. Trend • Scalability • Latency, Bandwidth • Attenuation, Phase Velocity • Distortion • Intersymbol Interference, Jitter, Cross Talks • Clock Distribution • Skew, Jitter, Power Consumption • IO Interface • Density • Impedance Matching • Cross Talks, Return loops

  7. II. Scalability: Interconnect Models • Voltage drops through serial resistance and inductance • Current reduces through shunt capacitance • Resistance increases due to skin effect • Shunt conductance is caused by loss tangent

  8. II. Scalability: Interconnect Models • Telegrapher’s equation: • Propagation Constant: • Wave Propagation: • Characteristic Impedance

  9. II. Scalability of Physical Dimensions b t w • R= p /A = p/(wt) • Z= ¼ (u/e)1/2 ln (b+w)/(t+w) • C= v Z • L= Z/v p: resistivity of the conductor u: magnetic permeability e: dielectric permittivity v: speed of light in the medium

  10. II. Scalability of Physical Dimensions • Resistance: Increases quadratically with scaling, e.g. p=2um-cm R=0.0002ohm/um at A=10umx10um R=0.02ohm/um at A=1umx1um R=2ohm/um at A=0.1umx0.1um • Characteristic Impedance: No change • Capacitance per unit length: No change • Inductance per unit length: No change

  11. II. Scalability of Frequency Ranges • RC Region • LC Region • Skin Effect • Loss Tangent

  12. II. Scalability of Frequency Ranges 1. RC Region e.g. on-chip wires R=2ohm/um(A=0.01um2) L=0.3pH/um, C=0.2fF/um R/L=0.67x1012

  13. II. Scalability of Frequency Ranges: RC Region ltr l Elmore delay model with buffers inserted in intervals ltr: length from transmitter to receiver l: interval between buffers rn: nmos resistance cn: nmos gate capacitance cg=(1+g)cn, g is pn ratio. rw: wire resistance/unit length cw: wire capacitance/unit length f: cd/cg

  14. II. Scalability of Frequency Ranges: RC Region Elmore delay model with buffers inserted in intervals Optimal interval Optimal buffer size Optimal delay

  15. II. Scalability of Frequency Ranges Example: w= 85nm, t= 145nm rn= 10Kohm,cn=0.25fF,cg=2.34xcn=0.585fF rw=2ohm/um, cw=0.2fF/um Optimal interval Optimal buffer size Optimal delay

  16. II. Scalability of Frequency Ranges: RC Region *no scattering, p=2.2uohm-cm

  17. II. Scalability of Frequency Ranges: RC Region • Device delay, rncn, decreases with scaling • Wire delay, rwcw, increases with scaling • Interval, l, between buffers decreases with scaling • In order to increase the interval, we add the stages of each buffer.

  18. II. Scalability of Frequency Ranges 2. LC Region

  19. II. Scalability 3. Skin Effect Skin Depth: e.g. 0.7um @ f=10GHz, p=2uohm-cm For 100umx25um RDC=0.000008ohm/um= 8ohm/m R= 0.000114ohm/um=114ohm/m

  20. II. Scalability 4. Loss Tangent

  21. References • E. Lee, et al., “CMOS High-Speed I/Os – Present and Future,” ICCD 2003. • http://www.itrs.net/Common/2004Update/2004Update.htm • G.A. Sai-Halasz G.A. "Performance Trends in High-End Processors,“ IEEE Proceedings, pp. 20-36, Jan. 1995. • M.T. Bohr, “Interconnect scaling-the real limiter to high performance ULSI” Electron Devices Meeting, 1995., International10-13 Dec. 1995 pp.241 – 244.

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