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Fast Network-on-Chip Simulator Using QEMU and SystemC for Enhanced Scalability and Retargetability

This paper presents a novel Network-on-Chip (NoC) simulator that integrates QEMU and SystemC to accelerate simulation processes, enabling effective design and testing of various NoC architectures. Traditional NoC designs at Register-Transfer Level (RTL) are often time-consuming and challenging to modify. Our proposed system facilitates full system verification by simulating CPU cores with QEMU and modeling NoC routers in SystemC. The simulator demonstrates significant improvements in simulation speed, achieving a 43% faster performance when distributed across dual-host computers, thus showcasing its scalability and retargetability for varying processor architectures.

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Fast Network-on-Chip Simulator Using QEMU and SystemC for Enhanced Scalability and Retargetability

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  1. National Sun Yat-sen University Embedded System LaboratoryA Fast Network-on-Chip Simulator with QEMU and SystemC Presenter: Min Yu,Lo Keita Nakajima, Takuji Hieda, Ittetsu Taniguchi. Hiroyuki Tomiyama, Hiroaki Takada 2012 Third International Conference on Networking and Computing

  2. What’s problem • NoC design • The design of NoCs at Register-Transfer-Level (RTL) is time-consuming. It is also very difficult to modify and/or change the network architecture if the design is not suitable for the target application. • NoC Simulator design • Availability(Simulation time ) • Scalability(Simulation of Various sizesNoC architecture) • Retargetability (Simulation of Various processor) • Full system verification

  3. FastNoC Simulator • This paper proposedNoC simulator • In the proposed simulator, each CPU core is emulated by a QEMU, and the network part including NoC routers is modeled with SystemC. • AcceleratedthisNoCsimulator • This NoC simulator can be executed on multiple host computers since the SystemCsimulator and QEMUs are connected via standard TCP sockets.

  4. Scalabilityand simulation time improvement • JPEG encoding application benchmark program. • Changed the number of cores on the NoC Simulator. • Simulated six NoC architectures(9,18,36,54,72,90,108). • Run this simulator on two host computers. • The distributed simulation on the dual host computers is 43% faster than the single-host simulation.

  5. Retargetability • Show this simulator supports any CPU core supported by QEMU since this use QEMU without modification. • In order to test the retargetability of the simulator, Changed the ISA of target cores and measured the simulation times.

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