1 / 17

Status – Week 274

Status – Week 274. Victor Moya. Simulator model. Boxes. Perform the actual work. A box can only access its own data, external data must come through signals (time!). The box manages its own signals. A box: whatever you do in 1+ cycle or whatever or what a piece of hardware does.

ivor-french
Télécharger la présentation

Status – Week 274

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Status – Week 274 Victor Moya

  2. Simulator model • Boxes. • Perform the actual work. • A box can only access its own data, external data must come through signals (time!). • The box manages its own signals. • A box: • whatever you do in 1+ cycle or whatever or • what a piece of hardware does

  3. Simulator Model • Signals. • Communication between boxes. • Carry the simulator time: 1+ cycle latency. • Parameters: bandwidth, latency. • Storage size: bw * (lat + 1). • Not allowed read and write with latency 0.

  4. Simulator Model • Wiring boxes: • Global static object. • Creates and binds signals by name. • Statistics • Global static object. • Boxes declare a statistic name. • The statistics object manages the different statitistics.

  5. Simulator Model SignalBinder BOX BOX Box StatisticBinder Signal Signal Signal Signal Statistic Statistic Statistic Statistic

  6. Simulator Model Box1 Box2 write read bw:2 lat: 3

  7. Problems • Must be 0 latency for wires forbidden? => NO! • What happens if a two boxes must communicate in the same cycle? => NOT ALLOWED!.

  8. Problems • How to manage multiple instances of the same Box (4 vertex shaders, 8 pixel shaders). • Create each instance as a different class with its own name and signal binding. • Box() now has a parameter Name that defines a different name for each instance (How can we grant the names are different?). • How to bind signals in multiple instanced boxed (VS, PS). • Signal are created/binded by the signal emiter and receiver. • Prefix signal name with instance name. • Add new parameters to Box() for the emiters name instances.

  9. Vertex Shader • VS 1.0 (NV20) based Vertex Shader model. • Multithread (multivertex?) supported. • No branching. • No texture/vertex buffer load. • No vertex kill.

  10. Vertex Shader

  11. Vertex Shader • VS 2.0+ (NV30) based Vertex Shader model. • Multithreaded?? Implemented with a FP array (3DLabs P10). • Dynamic branching. • No texture/vertx buffer load. • No vertex kill.

  12. Vertex Shader

  13. Vertex Shader • VS 3.0 (DX9.1). Not implemented yet. • Hardware implementation unknown. • Static and dynamic branching. • Texture/Vertex Buffer load (and store?). • Possible vertex kill?

  14. Vertex Shader Model • Instruction Fetch • Sends the instruction byte code pointed by the current PC to Decode/Register box (latency 1). • Decode/Register • Calculates next PC (sequential, jump, conditional jump, calls, return, indirect) and sends it to Instruction Fetch (latency 1). • Reads up to three source operands from the register files (Vertex Input, Constant, Temporary, Address) and sends them to Execute with the instruction operation code (latency1). • Gets incoming result (flags + operation result) from execute and write them in the register files (flags, Vertex Output, Temporary). • Execute • Performes an operation with the operands received with from the Decode/Register box and sends the result back to Decode/Register box with 1+ latency.

  15. Vertex Shader Model

  16. DirectX 9 • Almost ready. • DX 9 RC 0 just released. • ATI DX9 demos and drivers. • GDC Presentations are available already. • Introduction to VS/PS 3.0 and beyond.

  17. NV30 • Product ‘release’. • Cards in February. • Reviews in later December. • 400-500 MHz. • 0.13 um, 125 M Transistors. • FP array implements the vertex shader. • 8 pixel pipes, 1 TMU. • 128bit 500 MHZ DDRII.

More Related