FPGA firmware of DC5 FEE

1. FPGA firmware of DC5 FEE

2. Outline

3. List of issue • Data loss issue • Command error issue (DCM to FEM) • Command lost issue (PC with USB connection to GANDALF)

4. Module Connection Ethernet cable Optical fiber x8 x1 x20 Master CLK GANDALF DCM FEM Optical Tx Command & FLT Optical Rx Data …… FEM Signal and Clock rate — Optical Tx and Rx 3.1104Gbps — Master CLK 38.88 MHz (was 155.52MHz) — Command 38.88 Mbps (was 155.52MHz) — FLT (First level Trigger) Pulse sync to 38.88MHz CLK — Data 155.52 Mbps Totally 1 GANDALF 8 DCM 160 FEM

5. Clock Structure DCM FEM Rx clock 155.52M Deformater PLL1 FEM Ctrl Logic Xilinx Transceiver Clock 38.88M 77.76M GANDALF Optical Tx Optical Rx FEM2DCM transmit command 155.52MB 155.52M OSC 155.52M 233.28M PLL2 TDC 233.28M 90° 2M CMAD setting • Deformater is a VHDL code from T. Grussenmeyer. • Master 38.88MHz CLK is generated and phase adjusted by RX CLK and command from GANDALF. • Two TDC CLKs will be 233.28MHz = 38.88MHz x 6. (248MHz now) • 155.52MB is a phase adjustable CLK for data output.

6. First Level Trigger • In DCM, First level trigger is generated according to a specific command/data pattern from GANDALF. • A FLT pulse is distributed to FEMs sync to master CLK. Rx clock 155.52M Deformater Xilinx Transceiver Clock 38.88M GANDALF Optical Tx Optical Rx FLT(first level trigger) command

7. TCS Reset signal • TCS reset will be distributed to FEMs by a dedicated command sync to master CLK. • Not fully implemented yet. • A comment to FEMs to reset TDC counters in the current implemetation. • Need inputs about TCS Reset command/pattern from GANDALF.

8. FEM TDC Block Diagram x16 x16 Time CMAD x16 inputs Buffer Ctrl Logic Cycling buffer (512 hits) TDC x16 Flag x16 Reset # of TDC hits Command handler Write point Data Trig Flag x1 Trig Time Trigger Logic Trigger Match Event FIFO (512 x 32bit) DCM & FEM (8b/10b) Link logic Trig Flag Flag TDC FLT trigger Trig Time Reset It will be 4096x32 bit. 0100110110 Serial data

9. TDC counter • TDC value for each hit is 16 bit. • MSB 14 bit is from a counter by 233MHz CLK. • LSB 2 bit is determined by a four bit pattern latched with 233MHz CLK and 233MHz 90o CLK. 14 bits 2 bits 14 bits ≈ 70.3us 233.28M 233.28M 90°

10. Trigger Match • Time resolution • TDC time = 16 bit (1ns lsb) • Trigger Latency = 12 bit (4ns lsb) • Matching Window = 12 bit (4ns lsb) • (Ttrig–Tlatency–Twindow) < Thit < (Ttrig–Tlatency+Twindow) • Matching process stops at • 16 matched hits. • No more TDC hit left (Max hits for matching process is 255). • 4 unmatched hits after last matched hit. • All conditions will be adjusted according to the final noise level.

11. DCM block diagram x20 x20 x20 x20 x20 FLT(first level trigger) DCM & FEM (8b/10b) Receiver DCM to FEM Command FIFO FEM to DCM Data FIFO (512 x 32bit) FEM to DCM Frame flag FIFO DCM & FEM (8b/10b) Transmitter Command handler GANDALF DCM Link logic command 010011 Serial data data packing TCS info 010011 Serial data data Transceiver 010011 Serial data

12. DCM pack FEM data procedure Power on reset Idle Scan all FEM FIFO Any FEM frame valid frame valid No No Yes Yes Readout FEM data Wait 4 system clock No EOF word Timeout or all FEM valid No Yes Yes No All FIFO scan over Send S-link begin mark Yes Send S-link header Send S-link end mark

13. Data Loss issue(DCM to GANDALF) • Previous version of DCM FPGA design, the same state machine controls both command flow and data flow. • When a command arrives in DCM, the data packing and transmission will be interrupted and caused the data loss. • The latest DCM FPGA design is modified to have independent control for: • Command flow (GANDALF DCM  FEMs) • Data flow (FEMs  DCM  GANDALF)

14. Latest Data transmission Test(with new DCM firmware) 1. Pass command Trigger_on to DCM 2. DCM generates 100k trigger in one sec. • Test result • DCM did received 100k data frames from FEM. • The data stored in PC lost about 1.5% data frame. x1 x1 x1 GANDALF Optical fibre DCM Ethernet cable FEM USB Count mode 4. Packing data frame and pass to GANDALF 3. FEM send 1 data frame to DCM per trigger 7. Save data into file and use program analysis 6. Pass data frame to PC 5.Use counter check valid data frame number from FEM

15. Command Error issue(DCM to FEM) • A timing issue, long operational logic pathdue to • 8b/10b encoding • Multiplexing of commands and fill pattern • The latest DCM FPGA design add pipeline/FIFO to reduce logic path • Under test

16. Command lost issue(PC with USB connection to GANDALF) • When PC is taking data from GANDALF and sending commands to GANDALF at the same time, • DCM receives commands with error or loses commands. • Try to stop trigger first before sending commands.

17. Summary

19. Backup

20. Command lost (DCM to FEM) • Timing issue when do 8b10b encoder • Original structure 8b10b encoder Controller + Serializer ERROR command DCM to FEM Command FIFO 0101001100 Idle(K28.5) Trig func control Mode control control status

21. Fix Command lost (DCM to FEM) • New version DCM to FEM CMD FIFO CMD / idle Selector 32b to 8b FIFO 8b10b encoder CMD Serializer 0101001100 Mode select with command for DCM Trig mode func FLT pulse signal