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Firmware Update Progress Report for Jet FPGA

The firmware update for Jet FPGA is ongoing, with improvements in readout format, energy sum format, and clocking scheme to 160MHz. Preliminary testing at CERN expected before M4 deployment.

jacob-levine
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Firmware Update Progress Report for Jet FPGA

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  1. JEP status General  see Pawel • JEP system (no recent tests with readout/ROIB) • Jet FPGA firmware (ready) Sum FPGA • have been able to get the old ISE tools up again • working on the firmware update right now • readout format will be updated • backplane energy sum format will be updated • Re-work of RTDP and clocking scheme to 160MHz throughout • Latency optimized version post M4 • expecting initial version ready for first tests at CERN in the week before M4 • integration with Pawel's diagnostics will have to wait until a later date

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