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TOPIC : Test Vector Generation. UNIT 3 : Testing Faults and Test Vector Generation. Module 3.2: Fault Targeted Test Vector Generation. How to arrive at a test set?. A test set is to be developed that can detect any possible fault in the given circuit. There are two approaches:

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## TOPIC : Test Vector Generation

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**TOPIC : Test Vector Generation**UNIT 3 : Testing Faults and Test Vector Generation Module 3.2: Fault Targeted Test Vector Generation**How to arrive at a test set?**• A test set is to be developed that can detect any possible fault in the given circuit. • There are two approaches: 1) Random Test Generation (RTG) 2) Fault-targeted Test Generation (FTG)**Random Test Generation**• Take a random vector as test vector. • Calculate the performance of the circuit with & without faults. • Identify all the faults that can effect the output for this test vector. • Remove the covered faults from the fault list. • If there are some more faults in the fault list, take another random vector and repeat the process until the fault list becomes empty.**Fault-targeted Test Generation(FTG)**• Here we start with a vector which can detect a specified fault.**RTG & FTG**• The fault targeted simulation is a slow process initially compared to RTG. • If the number of faults is high, then a random test vector can detect more faults. If we use FTG then we need to generate a test for each single fault. • If the number of faults still left to be tested is less, then FTG is used. • Hence one adopts RTG in the initial stage when the number of faults to be tested are very high and when the number gets reduced, FTG is used.

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