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ATLAS/CMS pixel 65 workshop

This workshop brings together the ATLAS and CMS pixel detector communities for open discussions on developing next-generation pixel ASICs and detectors, essential for phase 2 upgrades. With anticipated needs for enhanced hit rates, radiation tolerance, and resolution, participants will explore novel designs using 65nm technology. The workshop will feature collaborative exchanges of ideas, outline requirements for phase 2 detectors, and promote joint efforts in engineering runs and chip designs. Join us to shape the future of pixel technology!

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ATLAS/CMS pixel 65 workshop

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  1. ATLAS/CMS pixel 65 workshop

  2. Why this workshop ? • Isn’t there enough pixel conferences/workshops/meetings/etc. ? • Answer: Yes but . . . • Get the ATLAS and CMS pixel detector/ASIC design communities together to have informal and open discussion on developing next generation pixel ASIC’s (and detectors) for phase 2 upgrades • Basic assumptions: • We will need new pixel detector upgrades in ~2020 • Higher hit rates: ~10x • Higher radiation: ~10x • Better resolution: 2-4x • Lower mass ?. • Hybrid pixel detectors because: • Extreme radiation tolerance: ~10MGy, ~1016neu/cm2 • Very high hit rates requires fast sensor and extensive data buffering and digital processing on pixel readout chip. • Sensor type not yet fixed: 2D Si, 3D Si, Diamond • 65nm technology choice • Density, radiation tolerance, access, cost , MPW ,

  3. Workshop content • Overview of Phase1 pixel chips • Requirements for phase2 pixel detectors • Initial ideas for phase2 pixel chips • 65nm technology: • Radiation tolerance • Initial experience in pixel community • Access • Design verification • ITN pixel proposal • So we just lean back (in these uncomfortable seats) and listen to all this and then that’s it ? • NO !

  4. Workshop WORK • Exchange of ideas and approaches • Define sketch of possible future collaboration: • 65nm technology: • Radiation qualification • Libraries (standard cell, memories, IO) • MPW, engineering runs, frame contract, support, tools , , • Analog building blocks • Pre-amp, Disc, biasing, DAC, ADC, PLL, , , • Digital • Architectures, Fault tolerance, • Simulation and verification environment • Building blocks • Common chips/runs: • Test chips • Shared engineering runs • One common chip for ATLAS/CMS • Short summary reports on possibilities to collaborate between across ATLAS - CMS Trains stop in the train-station Busses stop in the bus-station I have a work-station in front of me on my desk

  5. Practicalities • Agenda • Some late changes • Several talks not confirmed (but speakers present) • Several participants needs to leave Tuesday ~16:00 • Agenda “compressed” • Room: • Under refurbishment • Panic installation of video. • Coffee upstairs • Dinner ~19:00 • Participants: ~20 • Piattod’Oro • Rue du Cardinal-Journet 43, 1217 Meyrin • Google mapslink

  6. Prepare the pixel future orJust sit down and wait for apocalypse Dec. 21

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