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Lecture 6

Lecture 6. CES 522 Latches and Flip-Flops Jack Ou , Ph.D . Sequential Circuits. New output are dependent on the inputs and the preceding values of outputs. Characteristic: output nodes are intentionally connected back to inputs. Basic sequential circuits: Level Sensitive Circuits

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Lecture 6

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  1. Lecture 6 CES 522 Latches and Flip-Flops Jack Ou, Ph.D.

  2. Sequential Circuits • New output are dependent on the inputs and the preceding values of outputs. • Characteristic: output nodes are intentionally connected back to inputs. • Basic sequential circuits: • Level Sensitive Circuits • Edge Sensitive Circuits

  3. Small Perturbation to a Basic Inverter

  4. Large Perturbation to a Basic Inverter

  5. Application: SRAM is pulled below VS to force the cell to switch via regenerative action.

  6. Metastable Point

  7. Small Perturbation from the Metastable Point

  8. Intel’s Random Bit Generator

  9. Latches • Latches are level sensitive. • Latches propagate values from input to output continuously. • S sets Q =1; R sets Q=1 • Active low inputs are enabled by 0s. • Active high inputs are enabled by 1s.

  10. SR Latch with NOR Gates Active High inputs tPDSQ=2 NOR gate delays. tPDRQ_=1 NOR gate delay SR are trigger pulses which can return to zero once Q is set. Forbidden State

  11. SR Latch with NAND Gates Active low inputs

  12. D Latch

  13. D-latch Operation

  14. D-Latch (CK=0) D 0 0 0 DB

  15. D-Latch (CK=1) D D DB 1 D DB DB

  16. Analyze D Latch Using Boolean Algebra

  17. Transistor Level Implementation of D-Latch

  18. D-Latch (CLK=1,D=1) VDD 0 VDD

  19. Standard Library D LatchCLK=VDD (Q=D)

  20. Standard Library D LatchCLK=0V (Hold State)

  21. JK Flip-Flop

  22. JK Flip Flop (CK=0) 1 0 1

  23. JK Flip Flop (CK=1,J=K=0) 1 0 1 1 0

  24. JK Flip Flop (CK=1,J=K=1) 1 1 1 If CK is on for a long time, the output of this JK flip flip will toggle! The pulse width of CK must be less than the propagation delay time through the loop.

  25. JK Flip Flop (CK=1,J=0→1,K=0) 1 0 1 1 0 Current: Next:

  26. JK Flip Flop (CK=1,J=0 → 1,K=0) 1 1 0 1 1 0 Current: Next:

  27. CK=1, J=0 → 1, K=0 • Regardless of initial value of Q, • CK=1, J= → 1, K=0 will set the updated value of Q to a 1.

  28. JK Flip Flop (CK=1,J=0,K= 0→ 1) 0 1 1 1 0 Current: 0 Next:

  29. JK Flip Flop (CK=1,J=0,K= 0→ 1) 0 1 1 1→0 →1 0 1 Current: Next: 0

  30. CK=1, J=0, K=0 → 1 • Regardless of initial value of Q, • CK=1, J= 0, K=0 → 1 will set the updated value of Q to a 0.

  31. JK Flip-Flop J=1, K=1 can lead to oscillation if the width of CK is longer than propagation delay.

  32. JK Master-Slave Flip-Flop 1 1 1 0 The Q of the master latch is updated when CK=1. The slave latch is insulated from changes of J and K when CK=1 Q holds its current value.

  33. JK Master-Slave Flip-Flop (CK=1) 1 1 1 0

  34. JK Master-Slave Flip-Flop (CK=1) 1 1 1 1 1 0

  35. JK Master-Slave Flip-Flop (CK=1) 1 0 1 1 1 0

  36. JK Master-Slave Flip-Flop (CK=1) 1 1 1 0 1 0

  37. JK Master-Slave Flip-Flop (CK=1)

  38. JK Master-Slave Flip-Flop (CK=1)

  39. JK Master-Slave Flip-Flop (CK=1) 1 0 If J catches a glitch, it is stuck the master latch!

  40. Edge Sensitive Circuits

  41. JK Negative Edge-Triggered Flip-Flop 1 1 “hold” mode Disabled 1 Active-Low Devices

  42. JK Negative Edge-Triggered Flip-Flop 1 1 1 1 “hold” mode enabled 0 Active-Low Devices

  43. JK Negative Edge-Triggered Flip-Flop 1 1 “hold” mode enabled →disabled

  44. JK Negative Edge-Triggered Flip-Flop 1→1 1 1→1 1 hold→updatehold disabled→enableddisabled CK CK The NAND latch is only updated for a short interval immediately after the negative edge, before being set to the hold.

  45. Update

  46. J=0; K=1

  47. J=1; K=0

  48. Negative Edge Triggered Flip-FLop

  49. D Flip-Flop

  50. D-Flop X OUT samples IN at the positive edge of the clock 2 1 OUT=X 2: Track 2:hold CK of latch 2 CK of latch 1 1: Hold 1:track X=IN

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