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The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

This paper discusses the architecture, features, and implementation of the Octant Module for the ATLAS Level-1 Muon Trigger. It also covers the overlap handling and snapshot and test memory capabilities. Presented at the 12th Workshop on Electronics for LHC and Future Experiments.

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The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

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  1. The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface Stefan Ask, David Berge, Nick Ellis, Philippe Farthouat, Stefan Haas, Attila Krasznahorkay, Thilo Pauly, Georges Schuler, Ralf Spiwoks, Thorsten Wengler 12th Workshop on Electronics for LHC and future Experiments Valencia, Spain 26 September 2006

  2. Outline • ATLAS Level-1 Muon Trigger • Muon to Central Trigger Processor Interface • Architecture • Demonstrator • Muon Interface Octant Module (MIOCT) • Requirements & features • Block diagram • Implementation • Overlap handling • Snapshot & test memory • PCB layout • Summary LECC 2006, Valencia

  3. ATLAS Level-1 Muon Trigger RPCDetector Barrel Trigger Endcap Trigger TGC Detector RPC: Resistive Plate Chambers TGC: ThinGap Chambers FE Electronics FE Electronics On-detector Off-detector 144 Sectors (96 endcap & 48 forward) RPCSector Logic TGC Sector Logic 64 Sectors 2 Muon candidates/sector (pT, ROI, Q) Muon-CTP Interface(MUCTPI) Region-of-Interest (RoI) Muon candidates DAQ System (ROS) DAQ: ROS Level-2 Trigger (RoIB) Central Trigger Processor Level-1 Accept LECC 2006, Valencia

  4. MIOCT - Octant module Receive muon candidates from detector sector logic Resolve overlaps MIBAK - Backplane Multiplicity summing Readout data transfer Timing signal distribution MICTP - CTP interface Multiplicity output to CTP Trigger & timing signals MIROD - Readout driver Interface to LVL2 (RoI) and DAQ (event data) MIBAK Trigger MIOCT MIOCT MIOCT Readout 13 x 13 x 13 x + Timing + Binary Adder Tree 16 + MICTP CTP 208 Sector Logic inputs DAQ MIROD LVL2 MUCTPI Architecture LECC 2006, Valencia

  5. MUCTPI Demonstrator • Installed at point-1 since end 2005 • Integrated with CTP, RPC trigger, DAQ & LVL2 • Successfully used in combined cosmics runs • Redesign of MIOCT required for flexible overlap handling MICTP MIROD MIBAK MIOCT LECC 2006, Valencia

  6. MIOCT Functions • Input synchronization & alignment • Resynchronize sector data with system clock received from MICTP • Timing alignment of incoming sector words • Multiplicity calculation & overlap handling • Sum the number of muon candidates per pT • Avoid double-counting of single muons detected in more than one sector of an octant • Readout • Zero-suppression • Formatting and interface with MIBAK • Monitoring via VME • Constraints • Connectivity: 13 x 32-bit sector logic input • Latency: 3 BC for MIOCT, max. 8 BC for the MUCTPI LECC 2006, Valencia

  7. MIOCT Features • Sector logic inputs: • 32-bit parallel LVDS @ 40 MHz • Dual-stacked 2 x 68-pin VHDCI connectors • Twisted-pair SCSI-type cables • MIBAK readout: • 36-bit BusLVDS @ 40 MHz • Shared bus with token passing protocol • Trigger & timing signals from MIBAK: LVPECL • Multiplicity to adder tree on MIBAK: 18-bit LVTTL • Flexible overlap handling architecture • Look-up (LUT) table based, implementation in a single FPGA • Snapshot and test data memory for diagnostics and monitoring • Bi-directional sector logic LVDS buffers: allows sending data from memory to fully test other MIOCT modules and cables • Possibility to access the JTAG chains on all MIOCT modules in a crate via the Module Test and Maintenance (MTM) bus on the VME64x backplane LECC 2006, Valencia

  8. MIOCT Block Diagram VME MIOCT FPGA (EP2S90) VME Interface (EP2C5) VME Buffers Sector Logic LVDS Buffers BA31 BA32 BA01 BA02 EC47 EC00 EC01 MIBAK PECL Rx EC02 Timing Signals (BCK, L1A, etc.) EC03 EC04 FW00 Multiplicity (18) FW01 FW02 MIBAK Buffers Readout Data (36) D (72) A (19) Q (72) Services Power, JTAG, FPGA Config, SysMonitor, Board ID QDR-II SRAM (1Mx72) LECC 2006, Valencia

  9. Redesigned MIOCT 9U VME64x board 14-layer PCB Status Prototypes in October Series production planned for Q1’07 Sector logic LVDS buffers VME I/F Dual-stacked VHDCIconnectors QDRSRAM MIOCT FPGA (BGA1508) MIBAKBuffers MIOCT Evolution MIOCT demonstrator (2000) LECC 2006, Valencia

  10. Barrel-Endcap Overlap Barrel muon trigger chambers Overlapmuon Endcapmuontriggerchambers LECC 2006, Valencia

  11. Barrel-Barrel Overlap Barrel toroid LECC 2006, Valencia

  12. Overlap Region Geometry Barrel Sectors Endcap Sectors ForwardSectors Barrel-Endcap Overlap Barrel-Barrel Overlap LECC 2006, Valencia

  13. Functional blocks are implemented using look-up tables (LUTs) Overlap handling policy can therefore be easily changed via VME Overlap Handling Architecture 26 pT Values • Trigger path latency: 3 BC (including synchronization & alignment) • Internal operation at 4 x BCK (160MHz) pT Compare & Generate Suppress Candidate Flags EC-EC Overlap 12 Endcap Sector Candidates 20 EC-EC Overlap Flags 26 Suppress Candidate Flags BA-EC Overlap 32 BA-EC Overlap Flags Multiplicity Summing Multiplicity (6 x 3 bits) BA-BA Overlap 8 Barrel Sector Candidates 8 BA-BA Overlap Flags FW-FW Overlap 6 Forward Sector Candidates 8 FW-FW Overlap Flags LECC 2006, Valencia

  14. Snapshot & Test Memory • QDR-II SRAM • Independent DDR read & write ports (common address) • 4 times bandwidth • Source synchronous I/F • On-chip DLL • HSTL I/Os (1.5V or 1.8V) • Multiple vendors: Samsung, Cypress, NEC, ISSI, GSI, … Burst of 2 QDR-II SRAM read/write cycle • MIOCT snapshot & test memory • 2 x 1Mx36 chips: 128K BC per sector (~3.3ms) • 160 MHz DDR: ~23 Gbit/s read & write (~20Gbit/s required) • QDR-II SRAM controller IP core from Altera • Store data from sector logic and multiplicity/suppress candidate flags • Timing-in of the system and for diagnostics and monitoring • Replay sector logic data for test purposes (e.g. cable or self-test) LECC 2006, Valencia

  15. Routing between FPGA & QDR SRAM is critical: Impedance (50Ω) & length matching (~0.3”) required SI simulation (Cadence SpecctraQuest) used to validate termination scheme On-chip serial termination for read and write data Parallel termination on clock, address & control 416 sector input signals to FPGA PCB Layout MEM FPGA MEM • Long lines (>10”) from LVDS buffers near front-panel • Controlled impedance & series matching LECC 2006, Valencia

  16. Summary • MUCTPI • Interfaces 208 muon trigger sectors to the CTP • Calculates the muon candidate multiplicities for 6 pT thresholds • Avoids double counting of single muons detected in overlapping sectors of an octant • Working demonstrator system installed in ATLAS counting room, used for combined cosmic data taking runs • Redesigned MIOCT • Hardware implementation highly configurable using look-up tables in large FPGA • Allows seamless upgrade of existing system • Status • Prototypes in production • Series production (~40 modules) foreseen for Q1’07 • Questions? LECC 2006, Valencia

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