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Digital Design: Principles and Practices. Chapter 7 Sequential Logic Design Principles. Introduction. Combinational Logic Circuit Analogy: A heater with a heater-fan-speed selection knob Sequential Logic Circuit Analogy: A heater with up and down fan-speed selection buttons
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Digital Design:Principles and Practices Chapter 7 Sequential Logic Design Principles
Introduction • Combinational Logic Circuit • Analogy: A heater with a heater-fan-speed selection knob • Sequential Logic Circuit • Analogy: A heater with up and down fan-speed selection buttons • The state of a sequential circuit is a collection of state variables whose values at any one time contain all the information about the past necessary to account for the circuit’s future behavior. [Herbert Hellerman, Digital Computer System Principles, McGraw-Hill, 1967]
Introduction (cont’d) • For a three-speed fan, the state might be stored as two binary state variables. • 0: OFF • 3: the highest speed • A circuit with n binary state variables has 2n possible states. • Sequential circuits are sometimes called finite-state machines. • The state changes of most sequential circuits occur at times specified by a clock signal. • State changes at clock’s rising edge or falling edge
Clock Signals • Period • Frequency • Duty cycle • Microprocessors can have clock frequencies as high as 4 GHz. • Typical systems using TTL and CMOS parts have clock frequencies in the 5-500 MHz range.
Bistable Element • A bistable element has two stable states. • Two possible states: • Q = 0 • Q = 1
Bistable Element • The bistable element shown in Figure 7-2 has no inputs and therefore no way of controlling or changing its state. • When power is first applied to the circuit, it randomly comes up in one state or the other and stays there forever.
S-R Latch • S: Set Q = 1 • R: Reset Q = 0
Latches and Flip-Flops • Latches and flip-flops are the basic building blocks of most sequential circuits. • All digital designers use the name flip-flop for a sequential device that normally samples its inputs and changes its outputs only when a clocking signal is changing. (clocking signal: rising edge or falling edge) • Most digital designers use the name latch for a sequential device that watches its inputs continuously and can change its outputs at any time (although in some cases requiring an enable signal to be asserted.)
Propagation Delay • The propagation delay is the time it takes for a transition on an input signal to produce a transition on an output signal. • The propagation delay may be different depending on whether the output makes a LOW-to-HIGH or HIGH-to-LOW transition.
Propagation Delay, Rise, and Fall Time • Rise time: tr = time for a waveform to rise from 20% to 80% of its steady-state value (or 10% ~ 90%) • Fall time: tf = time for a waveform to fall from 80% to 20% of its steady-state value (or 90% ~ 10%) • Edge rate: trf= (tr + tf)/2 • Propagation delay time(the worst-case delay) (max-time): tpd = maximum time from the input crossing 50% to the output crossing 50% • Contamination delay time(the best-case delay) (min-time): tcd = minimum time from the input crossing 50% to the output crossing 50%
Propagation Delay, Rise, and Fall Time • Intuitively, we know that when an input changes, the output will retain its old value for at least the contamination delay and take on its new value in at most the propagation delay. • The gate that charges or discharges a node is called the driver and the gates and wire being driven are called the load. • Propagation delay time and contamination delay time • Output rising: tpdr / tcdr • Output falling: tpdf / tcdf
Propagation Delay Time (tpdr) (tpdf)
Minimum Pulse Width • Minimum-pulse-width specifications are usually given for the S and R inputs. • The latch may go into the metastable state and remain there for a random length of time if a pulse shorter than the minimum pulse width tpw(min) is applied to S or R.
Transmission Gate • When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call it a pass transistor. • By combining an nMOS and a pMOS transistor in parallel, we obtain a switch that turns on when a ‘1’ is applied to g in which ‘0’s and ‘1’s are both passed in an acceptable fashion. We term this a transmission gate or pass gate.
D Latch Design • Multiplexer chooses D or old Q
(Positive-Edge-Triggered) D Flip-Flop • When CLK rises, D is copied to Q • At all other times, Q holds its value • a.k.a. positive edge-triggered flip-flop, master-slave flip-flop
D Flip-Flop Design • Built from master and slave D latches
Edge-Triggered J-K Flip-Flop Q* = J．Q’ + K’．Q
Edge-Triggered J-K Flip-Flop • J-K flip-flops are not used much nowadays, but they are sometimes used in clocked synchronous state machines. • In designing clocked synchronous state machines, the next-state logic for J-K flip-flops is sometimes simpler than for D flip-flops. • However, most state machines are still designed using D flip-flops, because the design methodology is a bit simpler and because most sequential programmable logic devices contain D, not J-K, flip-flops. • Therefore, this book focuses on using D flip-flops.
