Download
a frequency synthesizer using two different delay feedbacks n.
Skip this Video
Loading SlideShow in 5 Seconds..
A Frequency Synthesizer Using Two Different Delay Feedbacks PowerPoint Presentation
Download Presentation
A Frequency Synthesizer Using Two Different Delay Feedbacks

A Frequency Synthesizer Using Two Different Delay Feedbacks

302 Vues Download Presentation
Télécharger la présentation

A Frequency Synthesizer Using Two Different Delay Feedbacks

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. A Frequency Synthesizer Using Two Different Delay Feedbacks Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 23-26 May 2005 page(s): 2799 - 2802 Vol. 3 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授

  2. Outline • Introduction • Architecture • Circuit Implementation • Simulation Results • Conclusion

  3. Introduction • The large dead zone induced by the PFD, it causes the phase error accumulation at the VCO output. • The jitter evoked by the inevitable 1/f and white noise of the circuits, it forces VCO to contribute phase noise toward the output. • The clock feedthrough and charge injection motivated by CP switches, it results in the abrupt vibrations on the VCO control line and their corresponding clock jitter even when the loop is locked.

  4. Two PFDs withseparate dead zones

  5. Conventional PLL architecture second-order low-pass filter

  6. The proposed PLL architecturewith double PFDs scheme

  7. The operations of the proposed PLL architecture

  8. The schematics of the delay cell PMOS input differential pair diode-connected transistors cross-coupled feedbacks current source

  9. The schematics of the ring oscillator

  10. The schematic of three-state PFD with delay buffers discard the spurs

  11. Charge pump circuit & Switch

  12. The schematic of the TSPC divider TSPC True Single Phase Clock 1. simple of structure 2. small dead zone

  13. Simulation results when Δt = 90ps

  14. Simulation results when Δt = 30ps

  15. Simulation results for the ring oscillator

  16. Transient responses of the PLLs settling time < 22μs

  17. The chip layout

  18. Performace summary of the proposed PLL

  19. Conclusion • A fully differential delay cell for the VCO is introduced to achieve wide locking range and low-jitter performance. • Two PFDs are combined to provide a less dead zone with a new phase-detecting approach and a less settling time. • A tunable delay element is used to suppress the ripple on the VCO control line, and hence a more accurate output clock can be resulted.