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A Low-Power High-SFDR CMOS Direct Digital Frequency Synthesizer

A Low-Power High-SFDR CMOS Direct Digital Frequency Synthesizer

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A Low-Power High-SFDR CMOS Direct Digital Frequency Synthesizer

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  1. A Low-Power High-SFDR CMOS Direct Digital Frequency Synthesizer Jinn-Shyan Wang; Shiang-Jiun Lin; Chingwei Yeh; IEEE International Symposium on Circuits and Systems,pp.1670-1673, 23-26 May 2005. 指導老師: 魏凱城 老師 學 生: 蕭荃泰 彰化師範大學積體電路設計研究所

  2. Outline • Abstract • Background and architecture design • The proposed low-power DDFS • Conclusions

  3. Abstract • A low-power high-SFDR CMOS DDFS, several design techniques. • Including a cell-basedlookup table, a power aware parameters selection method, areducedmultiplier, a speeded-up adder/subtracter,an extra pipeline stage, and supply voltage scaling.

  4. Background and architecture design The block diagram of a ROM-based DDFS with analog outputs.

  5. A low-power DDFS architecture for sine and cosine functions.

  6. The proposed low-power DDFS • A. Synthesized Lookup Table : Cell-based design can take full advantage of the shortened design time, circuit can be synthesized to meet different system requirements by specifying speed and power constraints.

  7. B. Selection of design parameters : Whenthe size of the multiplier is reduced, will be a nearly proportional reduction in power consumption, and the delay time is also reduced significantly.

  8. C. Voltage scaling : In this case, the power supply voltage VDD can be reduced to 2.1-V if the clock frequency is maintained at 100-MHz, and the power consumption can be reduced to 41.58-mW. • D. Reduced multiplier : The operation speed is also improved because of a shorter critical path, and therefore the voltage scaling approach can also be applied again to reduce the power consumption.

  9. E. Speeded-up adder/subtracter The k-bit input always arrives at the adder/subtracter before the j-bit input, so can use the concept of a carry select adder to speed up the addition process. fmax is increased to 152-MHz. Addition of a k-bit and a j-bit inputs.

  10. F. Pipelining In this design, only one pipeline stage is inserted after the multiplexers; with a VDD of 3.3-V, fmax is increased to 167-MHz. If the operating speed is maintained at 100-MHz, the supply voltage can be further reduced to 1.7-V.

  11. Conclusions • The six low-power techniques together result in the total power saving of up to 88.5%. • The proposed 1.7-V DDFS achieves a 98% enhancement in the power efficiency.

  12. Thank you !