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A low power ROM-less direct digital frequency synthesizer with preset value pipelined accumulator

A low power ROM-less direct digital frequency synthesizer with preset value pipelined accumulator

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A low power ROM-less direct digital frequency synthesizer with preset value pipelined accumulator

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  1. A low power ROM-less direct digital frequencysynthesizer with preset value pipelined accumulator Jun CHEN,Rong LUO,Huazhong YANG and Hui WANG IEEE International Symposium on Circuits and Systems, Jan 2006. 指導老師: 魏凱城 老師 學 生: 蕭荃泰 彰化師範大學積體電路設計研究所

  2. Outline • Abstract • Direct digital frequency synthesizer • Architecture of pipelined accumulator • Proposed preset value pipelined accumulator • ROM-less phase to amplitude converter • Simulation and Comparison • Conclusion

  3. Abstract • A preset value pipelined accumulator (PVPA) is proposed achieving update rates in excess of 500MHz by careful choice of the 12-7-7-6 4-stage pipelined architecture. • The modified Sunderland approximation and power-gating technique are used to reduce its area and power, respectively. • The design was implemented using a 0.18um CMOS technology, it occupies a core area of 0.04mm2 and dissipates 17.2mW at 1.8v supply voltage and 500MHz clock.

  4. Direct digital frequency synthesizer • DDFS made the technology popular in spread-spectrum communication, radar systems, test instrumentation, and electronic warfare. • In general, a DDFS consists of a phase accumulator, a phase to sine-amplitude converter (PSAC), a digital-to-analog converter (DAC), and a low-pass filter (LPF).

  5. fout = fclk*FCW/2M

  6. Architecture of pipelined accumulator m × L = M

  7. Proposed preset value pipelined accumulator

  8. ROM-less phase to amplitude converter When C is small enough

  9. Simulation and Comparison

  10. Conclusion • A preset value method is used to improve the operating speed of 32-bit 4 pipelined phase accumulator up to 500MHz, and no clock latency is introduced. • Power gating method is used to lower the power consumption of the PSAC. • Simulation results show that the average power is 17.2mW at 500MHz with a 70dBc SFDR in SMIC 0.18-μm CMOS technology.

  11. The end