A 1-V 2.4-GHz Low-Power Fractional-N Frequency Synthesizer with Sigma-Delta Modulator Controller

1. A 1-V 2.4-GHz Low-Power Fractional-N FrequencySynthesizer with Sigma-Delta Modulator Controller Shuenn-Yuh Lee; Chung-Han Cheng; Ming-Feng Huang; Shyh-Chyang Lee;Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on23-26 May 2005 Page(s):2811 - 2814 Vol. 3 Digital Object Identifier 10.1109/ISCAS.2005.1465211 指導教授 : 林志明 教授 學生 : 黃世一

2. Outline • Abstract • Introduction • Synthesizer architecture • Hardware implementation • Simulation and measurement results • Conclusion • References

3. Abstract • 1-V , 2.4GHz fractional-N frequency synthesizer with sigma-delta modulator controller for Bluetooth in 0.18 μm CMOS • dual-modulus divide-by-128/129 prescaler using dynamic D-flip-flop and operating clock frequency can reach as high as 2.6 GHz at 1-V • third-order feedforward sigma-delta modulator (SDM) ,division ratio and suppress the fractional spurs

4. Abstract • Tuning range of 2.136 to 2.53 GHz • Phase noise of -126.85 dBc/Hz at 1MHz offset • Core area without the SDM and the loop filter is 0.85 mm2 • Total power consumption 8.94 mW

5. Introduction • Bluetooth in the 2.4-GHz ISM band for short-range communication at medium data rate • Being intended for mobile operations, low power and low voltage • Frequency synthesizer in modern wireless communication system which consumes remarkable percentage of the transceiver power

6. Introduction • The high speed prescaler and VCO in the frequency synthesizer • Traditionally, prescaler with the bipolar or GaAs technologies, advanced standard CMOS process, low power consumption • In this paper, new optimized dual-modulus prescaler structure in 1-V 2.4-GHz fractional-N frequency synthesizer for Bluetooth • 0.18 μm CMOS technology

7. Introduction • The novel prescaler structure using dynamic D-flip-flop ,2.6 GHz at 1-V • HSPICE simulation ,the prescaler not only low-voltage and low-power but also can effectively reduce the synthesizer power dissipation • sigma-delta modulator(SDM), fractional spurs, suppress the in-band noise and improve the spectrum impurity

8. SYNTHESIZER ARCHITECTURE higher reference frequencies controls the instantaneous division modulus to produce a fractional mean division modulus

9. SYNTHESIZER ARCHITECTURE • The quantization noise can be shaped to higher offset frequencies and easily be filtered by the loop filter • High reference frequencies • Wider loop bandwidth • Faster switching time

10. HARDWARE IMPLEMENTATION A. Dual-modulus divide-by-128/129 prescaler three D flip-flops synchronous counter two NAND gates and several control logic gates asynchronous counter five toggle-flip-flops

11. The operating speed of prescalers is mainly limited by the synchronous counter • References [1] ~ [4] increase the operated speed • Most flip-flops based on the True-Single-Phase-Clocked (TSPC) dynamic DFF’s in [5] • TSPC : one single clock signal to achieve high speed operation

12. To maximize the speed of the divide-by-4/5 synchronous counter one DFF, one NAND-FF, and one NOR-FF reduce the discharge path efficiently reduce the propagation delay and improve the speed of the synchronous counter.

13. In order to increase the speed of synchronous counter in the low voltage design [6]

14. B. Voltage-controlled oscillator (VCO) In order to achieve the required tuning range and overcome the phase noise, a differential structure as shown in Fig. 5 has been adopted for the better rejection of common-mode additive noise.

15. C. Phase frequency Detector (PFD) The PFD produces short pulses at both output nodes in every reference period even if the synthesizer is locked, and the pulses will modulate the VCO if there is a mismatch among the pump currents of NMOS and PMOS

16. D. Charge pump (CP) and loop filter (LF) To combat thecharge injection, one effective solution adopting the opampas Vcont buffer is employed to maintain the voltage level. The CP including two unity gain amplifiers can reach the voltage tracking range with rail to rail and the nominal CP current is 1mA in our design

17. E. Third-order FFD Sigma-Delta Modulator by Verilog HDL The word length of the accumulators in the modulator is chosen as 5 bits

18. SIMULATION AND MEASUREMENT RESULTS

22. CONCLUSION

23. References • [1] R. Rogenmoser, Q. Huang, and F. Piazza, "1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 µm CMOS prescalers," in Pro. IEEE Custom Integrated Circuits Conference (CICC), 1994, pp. 387-390. • [2] C.Y. Yang, G.K. Dehng, J.M. Hsu, and S.I. Liu, "New dynamic flipflops for high-speed dual- modulus prescaler," IEEE J. Solid-State Circuits, vol. 33, pp. 1568-1571, Oct 1998. • [3] S.H. Yang, C.H. Lee, and K.R. Cho, "A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop," in Proc. 14th Annual IEEE International, ASIC/SOC Conference, 2001, pp.276-280. • [4] G.K. Dehng, C.Y. Yang, J.M. Hsu, and S.I. Liu, "A 900-MHz 1-V CMOS frequency synthesizer", IEEE J. Solid-State Circuits, vol. 35 Issue: 8, pp. 1211-1214, Aug. 2000. • [5] J. Yuan and C. Svensson, "High-speed CMOS circuit technique,“ IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62 -70, Feb. 1989. • [6] W. Yun, S.H. Yoon, and J.W. Chong, "New high speed dynamic Dtype flip flop for prescaler," in Proc. IEEE International Symposium on Industrial Electronics (ISIE), 2001, pp. 629-631. • [7] Tai-Haur Kuo, Kuan-Dar Chen, and Jhy-Rong Chen; "Automatic coefficients design for high-order sigma-delta modulators," IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46 , Issue 1, pp. 6-15, Jan. 1999.