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Proposal of CSP based Network Design and Construction

Proposal of CSP based Network Design and Construction. Kazuto Tanaka ,Satoshi Iwanami ,Takeshi Yamakawa, Chikara Fukunaga （ Tokyo Metropolitan University) Kazuto Matsui （ Prominent Network inc. ） Takashi Yoshida （ Smart Scape inc. ）. SpaceWire Network as a parallel system.

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Proposal of CSP based Network Design and Construction

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  1. Proposal of CSP based Network Design and Construction Kazuto Tanaka ,Satoshi Iwanami ,Takeshi Yamakawa, Chikara Fukunaga（Tokyo Metropolitan University) Kazuto Matsui（Prominent Network inc.） Takashi Yoshida（Smart Scape inc.） k.tanaka SpW Conf. at Nara

  2. SpaceWire Network as a parallel system • Parallel system with many processors and front-end devices • Extremely strict care to avoid resource conflicts and deadlocks for system design processor1 sensor3 sensor1 sensor2 processor2 k.tanaka SpW Conf. at Nara

  3. processor1 sensor3 sensor1 sensor2 ：channel communication processor2 ：process CSP（Communicating Sequential Processes） • A formal design method for parallel processing systems • Parallel processing with channel communications • Synchronization of processes • Data sharing through channels between processes • No shared memory between processes • Refinement with mathematical deduction • Check possible failures (livelock, deadlock) k.tanaka SpW Conf. at Nara

  4. Router Network System(IEEE1355) • Network on an FPGA chip • Components • TPCORE (processor) • OD convertor (protocol convertor) • Router (link switch unit) FPGA IEEE1355 ・ ・ ・ OD convertor TPCORE 1 OD convertor TPCORE 0 Router OD convertor TPCORE 2 ・ ・ ・ ・ ・ ・ * We regard SpW and IEEE1355 are almost identical for the moment k.tanaka SpW Conf. at Nara

  5. TPCORE • Processor (homemade 2003) • Clock frequency : 24MHz • Instruction set compatible with transputer (Inmos ltd., UK) • Parallel processing with Occam (language) without Operating System • Flexible networks (on a FPGA chip) with four external I/Fs (OS-Link) • OS-Link is a simple bit serial link • No destination address in OS-Link R Host PC Host PC Host PC TP0 TP2 TP0 TP0 TP2 TP3 TP1 TP3 TP1 OS-Link :process tree mesh k.tanaka SpW Conf. at Nara

  6. OS-Link and IEEE1355（DS）-Link • OS-Link • Simple protocol • No destination address • IEEE1355(DS)-Link • Complex protocol, layered structure (packet , character (= token )) • Header contains destination address IEEE1355(DS)-Link OS-Link ・・ ・・ ・・ ・・ ・・ ・・ ・・ ・・ end of message data ・・ ・・ header end of packet data 2 start-bit 1 end-bit 1parity-bit 1 control or data select bit k.tanaka SpW Conf. at Nara

  7. OD-convertor • OS to DS and DS to OS conversion • Main components • FCC (Flow Control Character) –rx ,FCC-tx • Flow control for communication character transmission of DS-Link protocol • DS selector • Selection of FCC or other character (both directional) OD convertor（DO convertor） DS selector FIFO DS tx DS-Linkout OS-Linkin character OS rx FCC FCC-rx FIFO OS-Linkout DS rx DS-Linkin character Parity check OS tx FCC FCC-tx k.tanaka SpW Conf. at Nara

  8. Router • Components • DS-analyzer • Pick up the destination address from header of input packet • FCC and character transmission and DS selector • Crossbar (Xbar) • Connection to the destination channel (bidirectional) Router Xbar control OD DS analyzer TPCORE 1 Xbar DS analyzer OD TPCORE 0 DS analyzer OD TPCORE 2 : destination address k.tanaka SpW Conf. at Nara

  9. OS DS DS OS Time Sequence of the Network • Packet transmitted by TPCORE0 (OS-Link) • Converted to DS-Link by OD convertor • Router switch • Reverted to OS-Link • Data accepted by TPCORE2(OS-Link) OD OD OS OS TP0 TP2 DS Router DS example of packet transfer：address=2,data=FF 3.32 μｓ k.tanaka SpW Conf. at Nara

  10. Summary • Network-Router and OD convertor (IEEE1355) have been designed based on CSP. • By refinement checking ,We find no deadlock , no livelock in these devices as a parallel system. • Detailed discussion of CSP will be found in our another presentation (Poster). • Correct data communication has been confirmed using TPCOREs. • We measured DS-Link transfer rate . It is 20.29Mbps. Theoretical value is 20.28Mbps . • The difference is less than a clock width (48MHz). • The good agreement has been achieved. • From this study, we found CSP as a good design method for parallel systems. Thank you for your attention !! k.tanaka SpW Conf. at Nara

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