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Literature Review

Literature Review. A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) —— Yiran Chen, et al. Fengbo Ren. 09/03/2010. Background. STT-RAM: Spin Transfer Torque Random Access Memory Key memory device: magnetic tunnel junctions (MTJ)

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Literature Review

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  1. Literature Review A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM) —— Yiran Chen, et al. Fengbo Ren 09/03/2010

  2. Background • STT-RAM: Spin Transfer Torque Random Access Memory • Key memory device: magnetic tunnel junctions (MTJ) • Utilizes the spin-transfer torque phenomenon • Most existing memory technology is greatly challenged beyond 45 nm • SRAM: high power consumption, leakage increasing 10X with each technology node • DRAM: refresh current increasing, capacitor element hardly can maintain the necessary charge. • Flash: limited endurance, high write power, very slow write speed. • Need for universal memory Anti-parallel Parallel RP RAP

  3. Memory Technology Comparison • STT-RAM combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance.

  4. Problem • Reference scheme of reading operation is a design challenge. • Conventional reading • Applying a read current IR • Generate VBL,L and VBL,H on BL • Compare BL voltage with VREF • Process variation on tunnel barrier’s thickness • Resistance variation RL/RH Read current IR RTR

  5. Motivation • The current dependence of the high and the low resistance states of an MTJ are quite different. • the current roll-off slope of the high resistance state is much steeper than that of the low resistance state. Nondestructive Self-reference Scheme RAP ± δ RREF RP

  6. Read Circuit & Its Operation Current Source • First read • A read current IR1 is applied to generate BL voltage VBL1 and stored in C1 • Second read • Another read current IR2 (β= IR2/ IR1) is applied and generates VBL2. • Sensing • VBL1 and VBL2O are compared Memory Cell Voltage Divider Ratio = α Sense “1” Sense “0”

  7. Robustness analysis • A 16kb testing chip is fabricated with TSMC 0.13μm technology • 3 factors that affect the robustness • The variation of read current ratio β = IR2/IR1 • The shift of the NMOS transistor resistance RTR under IR1 and IR2 • The variation of voltage ratio α of the voltage divider.

  8. Conclusion • Interesting idea • Contribution • A novel self-reference read scheme of STT-RAM to overcome the large bit-to-bit variation of MTJ resistance is proposed. • The robustness analysis shows that the proposed scheme requires restrict control on the device variation and mismatch, with relatively small sense margin. • Performance and energy overhead has to be analyzed for practical design.

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