IDV Integrated Design and Verification Chalmers 12-May-2006

1. IDVIntegrated Design and VerificationChalmers 12-May-2006 Emily Shriver Research Scientist Strategic CAD Labs, Intel

2. Outline • Brief introduction to IDV • IDV demo • Design and Verification Together • Abstract RTL  Detailed RTL  To Netlist  To Layout • break • Demo Continued • IDV - from 50,000ft (or 120,000m) – grand vision

3. Myself • Since 2002 in a CAD research group at Intel • Power Reduction Identification • Using functional analysis and formal methods to automatically identify opportunities to reduce power. • IDV – Integrated Design and Verification • Use IDV to refine 64 bit IEEE Floating Point HLM to RTL implementation • Path finding: How to get IDV used in a design team? • >55 designers using IDV (micro-architects and circuit designers) • Static Timing Analysis • How fast does the design go? • CAD tool AD and development for Alpha 21164, 21264, 21364 • Timing Methodology co-lead for Alpha 21364 • Gate Level simulation – event driven and cycle-accurate • University of Michigan – Thesis Advisor Karem Sakallah • Concentration VLSI • Carnegie Mellon University - undergraduate • Electrical Engineering, Computer Engineering, & Mathematics

4. IDV – A Brief Overview • Today Designing and Validation of the Design are done by two separate teams “almost independently” of each other. • Validation is in the critical path to getting a design to market. • Due to Moore’s law, with each process generation, ~2x more logic to validate – but the bug rate is increasing exponentially not linearly. • IDV combines both the Designing of the chip and the Verification of the chip – therefore • reducing the number of bugs introduced in the design

5. Design and Verification Together Validation • Transformations (Refinements) to Change the design from the HLM to the Layout. • Each step is maintained Logically Equivalent to the previous. • Note: This Picture is identical to the Picture Emil Axelsson showed in Tuesday’s Lecture with respect to Wired. HLM abstraction RTL RTL Circuits/ Netlist ECO Layout

6. Transformation step Verification step M1 M2 M2 M4 M5 Schematics Another Way to Look at It Validation 50k HLM Tool guarantees that only valid transformations and/or verification steps are performed

7. Today’s Demo – RTL to Layout • Pros: The Abstract (starting) RTL • Natural from a human perspective • Make it easier to “get the specification correct” • Often small • Cons: The Abstract RTL • May use constructs that are expensive to implement • (e.g. adders instead of muxes) • synthesis can’t automatically do a good job on • This demo focuses on transforming the Abstract RTL into a design… • with a completely different implementation • that improves synthesis results (timing, power) • So a human will produce better timing & power • By using retiming, Shanoning, Logic splits RTL RTL Circuits/ Netlist Layout

8. Problem Description • The IQ (instruction queue) is an 18 entry cyclical queue. • At every cycle up to 6 new entries from the IFU (Instruction Fect Unit) can be put into the IQ (queue) • At every cycle up to 5 entries are released from the IQ (queue). • The IFU, writes data to the IQ, should stall writes (stop writing) if there are less the 6 free entries in the IQ. • We will implement a mechanism which creates the stall signal. (Called IQ6Empty) The Red Box Instructions Release Entries IFU New Entries Num New Entries Num Released IQ empty IQ 18 entries IQempty

9. Problem Description (Cont.) • Inputs : • Num New Valid Inputs : 7 Bit Wide Mutex Signal donating the number of new IFU valid inputs (0 to 6) • Num Release Entries : 6 Bit Wide Mutex Signal donating the number of entries released from the IQ. • Clear Signal : Donates a situation where the entire IQ queue is cleared. • Output: • IQ6Empty : A stall signal to the IFU, donating a situation where we have less than 6 free entries in the IQ.

10. (5 FFs) Num New Valid Inputs encode 5 bit Adder Num Release Entries encode 5 Bit Subtract Abstract RTL

11. Constraints on Implementation • Timing considerations : • Num Release Entries is a critical timing path • New Valid inputs are critical but not as critical as Release • Clear is not critical • Muxes Library cells are inverting (for optimal synthesis)

12. ImplementationVersion 1 Num New Valid Inputs Prepend ‘0 Num Release Entries

13. RTL vs Implementation • Implementation is totally different • Muxes vs Adder & Subtractor • 5 States vs 24 states • Comparator vs Inverter • Timing paths from release control is considerably eased. • RTL: Release to IQ6Empty path Subtract  Mux  Compare • Imp: Release to IQ6Empty path Mux  Inverter • Clear location changed (FEV comparable to RTL. This is because after clear, releasing entries has no effect in both RTL and Implementation)

14. Getting a SPEC into IDV • HFL • Syntactic sugar • A hardware description layer built on top of reFLect • Have full power of reFLect functional language • RTLs • Verilog, System Verilog • Layout

15. HFL – The Abstract RTL TYPE bv4 = bitvector(4); TYPE bv5 = bitvector(5); TYPE bv6 = bitvector(6); TYPE bv7 = bitvector(7); let find_first bv = letrec ff (b:bs) cnt = IF b THEN cnt ELSE ff bs (cnt '+' '1) /\ ff [] cnt = cnt in ff (rev (tobits bv)) '0 ; let iqemtpy = INTERFACE bit_input clk. bv7_input newValid. bv6_input newRelease. bit_input clear. bit_output iq6empty. bv5_signal newValidCount newReleaseCount currentCount currentPlusNew currentMinusRelease newTotalCount zero twelve.

16. HFL – getting a design into IDV CELL "iqemtpy" ( nVmutex IS_ASSERTION (strong_mutex newValid) # nRmutex IS_ASSERTION (strong_mutex newRelease) # no_underflow IS_ASSERTION (newReleaseCount '<=' currentPlusNew) # now_no_overflow IS_ASSERTION (currentCount '<=' '18) # next_no_overflow IS_ASSERTION (newTotalCount '<=' '18) # newValidCount <== find_first newValid # newReleaseCount <== find_first newRelease # add2 newValidCount currentCount currentPlusNew # sub2 currentPlusNew newReleaseCount currentMinusRelease # MUX clear zero currentMinusRelease newTotalCount # gnd zero # ff clk newTotalCount currentCount # leq2 newTotalCount twelve iq6empty # constant "0c" twelve ); //store_fub "SPiqempty_demo2" (iqemtpy 'clk 'newValid 'newRelease 'clear 'iq6empty);

17. Proof Spec – part 1 • Load Design • Expand (flops) 5 bits to 32 bits • Add explicit wire. • Replace w/library element - wire with an “identity operation”  5to32bit decoder with 32to5bit encoder. • Retime 5to32bit decoder backwards  32 flops • Replace Compare <= 12 with invert of bit 12. • Sel Cmp/Prop/Const/decode. Transform editor. Add inverter of bit 11. Cut compare. FEV fail. Counter Example. Instead bit 12. FEV succeeds. • Rename Wires - 0newCount – 1newCount • Reduce 32 flops to 24 flops • Sel Prop/decode. Add assertion top 8 bits always zero (use transform editor) • Sel flops/azero. Split the flops, select top 8 flops, xform editor to cut flops, then add ground on out sigs, remove always zero, verify • Remove top unused • Change Adders/Subtract to Shift & Case Statements • Add property: assume valid count do by Replace – • Retime forward assume value • Show HFL description. Then use Replace. • Add buffer pairs. • Synth shifters. Replay rest.

18. Layout • Once the Design is mapped to cells can use IDV to layout the design. • Mux demo.

19. Observations • We transformed the abstract RTL into a totally different implementation and then produce layout. • The abstract RTL is verified logically equivalent to the implementation and to the layout. • We can compare implementations for Timing/Area/Power.