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FlowMap: A Groundbreaking Algorithm for Delay Optimisation in FPGA Design

This paper explores FlowMap, an innovative algorithm developed for depth optimisation in FPGA designs, originally published in 1992 and awarded in 1994. FlowMap addresses the NP-hard problem of depth minimisation, offering a polynomial-time solution. This algorithm is crucial for efficient FPGA compiler design, demonstrating significant improvements in LUT network size and delay. The presentation covers the algorithm's fundamentals, its enhancements, and practical results, fostering discussion on its implications in the field of programmable hardware design.

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FlowMap: A Groundbreaking Algorithm for Delay Optimisation in FPGA Design

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  1. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimisation in Lookup-Table Based FPGA Designs Presented by Qiwei Jin 10/09/2014

  2. Overview • The paper and the authors. • Some background information. • The algorithm in detail. • Results and Conclusion. • Questions for discussion.

  3. About the Paper • Originally published in 1992, won IEEE Circuit & Systems Society best paper award in 1994. • 238 citations in total, 33 self. • The firstalgorithm to solve a conventionally NP-hard depth minimisation problem in polynomial time. • The algorithm is a key component in most commercial FPGA compilers. • FlowMap-r and other more sophisticated algorithms published by the authors at the same year or later for both depth and area minimisation.

  4. Jason Cong • Chairman of Computer Science Department, UCLA. • Was Assistant Professor in 1994 when this paper was published. • Got Promoted to Associate Professor in the same year. • His company Aplus was acquired by Magma in 2004 for "$13 million in stock, cash and incentives“. Picture borrowed from Jason Cong’s homepage

  5. Yuzheng Ding • Very low profile person, no picture, no home page, not even on FaceBook. • RA in UCLA for PhD when this paper was published. • May have left university for work (Mentor Graphics) after graduation. • Still working actively with Jason Cong, latest paper published in year 2008.

  6. Background • FPGA (Field-Programmable Gate Array): Programmable hardware. Xilinx Virtex 5 FPGA

  7. Background Cont. For more information, go to Wayne Luk’s Custom Computing Course

  8. Background Cont. • FPGAs are essentially a bunch of wires and LUTs (Look-Up Tables) that can be configured to emulate the behaviour of a digital circuit. • FPGAs can be configured by Hardware Description Language (HDL, such as VHDL). • Based on the HDL, a netlist can be generated automatically by some algorithm (FlowMap!).

  9. Background Cont. = 4-Input 1-Output LUT (16 entries in total)

  10. Background Cont. • Mappings from ASIC to FPGAs are not necessary one to one. • The question is how to achieve the optimal condition? =

  11. Background Cont. • Trade-offs: • Area (number of LUTs used) • Depth (delay of the circuit) • FlowMap focuses on depth optimisation depth

  12. Depth Minimisation Example

  13. The Key Idea of Depth Minimisation • Try to pack as many gates in different levels into a LUT as possible. • Number of LUT used (Area) is not the primary concern. • The problem is equivalent to generating optimal code for expressions containing common subexpressions, hence NP-Hard.* • Conventional method will decompose the Boolean network into a forest of trees before processing. • FlowMap can find an optimal mapping directly from a Boolean network within polynomial time. Let’s see how. * A. Aho, S. C. Johnson, “Optimal Code Generation for Expression Trees”, 23, 3, 488-501 (1976).

  14. Preliminaries • Input(T) • Cut (X, X) • Node Cut Size • Edge Capacity • Edge Cut Size • Whether a cut is K-feasible • Height of a Cut

  15. The FlowMap Algorithm • 2 Phases • Node Labeling: define the optimal depth of the LUT mapping solution for Nt. • LUT Mapping: generate the LUT network based on the labeling in the first phase.

  16. Phase 1: Node Labelling

  17. Phase 1: Node Labelling Cont.

  18. Phase 2: LUT Mapping

  19. Phase 2: LUT Mapping Cont.

  20. The FlowMap Pseudocode

  21. Enhancements • Maximising Cut Volume During Mapping • Postprocessing (flow-pack) Operations to reduce number of K-LUTs

  22. Results

  23. Conclusion • The paper presents the first algorithm to compute a NP-hard problem in polynomial time. • Compared to other algorithms FlowMap is about to reduce up to 7% of the LUT network and reduce up to 50% of the number of LUTs.

  24. Questions • It is claimed that a minimum height K-feasible cut can be found in O(Km) time, where K is the number of input of LUT and m is the number of edges of in the network. • But it is not clear to me how it is derived.

  25. Questions Cont. • It would be interesting to see the time taken to compute the mapping for the testing cases with FlowMap vs. Other Algorithms. • The testing cases are generally small in size, it would be more convincing to see some large size examples.

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