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SCIPP R&D on the International Linear Collider Detector

This review discusses the current R&D activities at SCIPP for the International Linear Collider (ILC) detector, including physics and machine studies, detector resolution standards, silicon tracking capabilities, and proof-of-principle for low-noise silicon strip readout.

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SCIPP R&D on the International Linear Collider Detector

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  1. SCIPP R&D on the International Linear Collider Detector SCIPP Review May 18, 2006 Presenter: Bruce Schumm

  2. R&D Activity is increasing, with studies now on four fronts: • Physics and machine studies for e-e- running • Detector resolution standards from physics simulation • Reconstruction capabilities of all-silicon tracking • Hardware proof-of-principle of low-noise silicon strip readout Current involvements (all very much part time) 3 senior physicists, 1 post-doc (looking for a second), 8 (current) undergraduate students, 1 engineer, 2 technical staff, one bored spouse of a Silicon Valley engineer.

  3. International Linear Collider: Activity on the e-e- Front • Clem Heusch is the SCIPP participant in e-e- studies • Leading international effort in the use and application of e-e- beams at the ILC • Continuing series of workshops hosted by SCIPP; proceedings published in World Scientific • Heusch is a member of ILC Subcommittee on International Collaboration.

  4. Detector Resolution Standards from Selectron Production Participants: Senior Physicist Bruce Schumm Undergraduate Thesis Students Sharon Gerbode, Heath Holguin,Troy Lau*, Paul Moser, Adam Perlstein, Joseph Rose, Matthew Vegas Community Member (on hold before Grad School) Ayelet Lorberbaum *Recipient of two Undergraduate Research Awards; grad school at U. Michigan.

  5. Motivation To explore the effects of limited detector resolution on our ability to measure SUSY parameters in the forward region (“benchmark process” study). SiD Tracker

  6. Determine the selectron mass accuracy in both the central (0 < |cos| < .8) and full (0 < |cos| < 1) region

  7. Simulation of SiD Tracking System (and SiD variants) Participants: Senior Physicist Bruce Schumm Recent Graduate Students Christian Flacco, Michael Young* Undergraduate Students John Mikelich, Tyler Rice, Lori Stevens, Eric Wallace *Supported primarily through department (TA) funds; SLAC paid for ½ of his support this summer.

  8. Simulation of SiD Tracking System, continued Three areas of work: Fast MC Simulation Billior-based LCDTRK.f (B. Schumm) provides covariance matrices for fast MC simulation and resolution plots. SiD Tracking Capabilities Explore tracking performance of SiD tracker and variants Microstrip Pulse Development Simulation Provides simulation of pulse development and amplification for designing and detector layout

  9. LCDTRK.f comparison of SiD options with TESLA (LDC) design, from Snowmass 2005

  10. CURVATURE ERROR vs. CURVATURE Standard (Original) Code

  11. Pattern Recognition Capabilities of an All-Silicon Central Tracker Can one do pattern recognition with only five central tracking layers? Might more layers improve performance to an extent that justifies the extra material? SiD Tracker Current code: Nick Sinev, U. Oregon

  12. EFFICIENCIES FOR QQBAR EVENTS Doesn’t look that spectacular; what might be going on here?

  13. Of course! The requirement of a VXD stub means that you miss anything that originates beyond r ~ 3cm. This is about 5% of all tracks. With current “VXDBasedReco” algorithm, we won’t get the ~5% of tracks that originate beyond 2cm.

  14. Outside-in Tracking (Eric Wallace) Circle-fit tracker (Tim Nelson, SLAC) developed at Snowmass Eric has optimized this algorithm for finding non-prompt tracks after hits from VXDBasedReco tracks are flagged Remaining tracks found with ~80% efficiency All remaining tracks Found Not found Radial Origin (mm) Essential tool for SiD tracker optimization.

  15. Pulse Development Simulation Long Shaping-Time Limit: strip sees signal if and only if hole is col-lected onto strip (no electrostatic coupling to neighboring strips) Include:Landau deposition (SSSimSide; Gerry Lynch LBNL), variable geometry, Lorentz angle, carrier diffusion, electronic noise and digitization effects

  16. Result: S/N for 167cm Ladder

  17. Electronics Simulation Detector Noise: From SPICE simulation, normalized to bench tests with GLAST electronics Analog Measurement: Employs time-over-threshold with variable clock speed; lookup table provides conversions back into analog pulse height (as for actual data) RMS Gaussian Fit Essential tool for design of front-end ASIC Detector Resolution (units of 10m)

  18. The SCIPP/UCSC ILC HARDWARE GROUP Faculty/Senior Alex Grillo Hartmut Sadrozinski Bruce Schumm Abe Seiden Students Greg Horn Glenn Gray Bryan Matsuo (Comp.Sci.) Post-Docs [Gavin Nesom*] Jurgen Kroseberg Lead Engineer: Ned Spencer Technical Staff: Max Wilder, Forest Martinez-McKinney *Recently lured away by the sirens of Silicon Valley

  19. The LSTFE-2 ASIC Process: TSMC 0.25 m CMOS 3 s shaping time; analog readout it Time-Over-Thres-hold with 400 nsec clock

  20. 128 mip 1 mip Operating point threshold Readout threshold 1/4 mip

  21. INITIAL RESULTS LSTFE-2 chip mounted on readout board FPGA-based control and data-acquisition system

  22. 0.80 fC 0.46 fC Comparator S Curves Vary threshold for given in put charge Read out system with FPGA Get 1-erf(threshold) with 50% point given response, and width giving noise 1.11 fC 1.42 fC 1.73 fC 2.04 fC

  23. Gain and Noise Results (Load = 150 pF, or about a 115 cm detector) “Noise referred to input” is in equivalent electrons Result: ~5300 electrons noise Expectation: ~1400 electrons noise Picoprobe studies isolate problem to shaper stage  Redesign getting underway

  24. DIGITAL ARCHITECTURE: FPGA DEVELOPMENT Digital logic should perform basic zero suppression (intrinsic data rate for entire tracker would be approximately 50 GHz), but must retain nearest-neighbor information for accurate centroid.

  25. Li Hi Li+1 Hi+1 Li+2 Hi+2 Li+3 Hi+3 Li+4 Hi+4 Li+5 Hi+5 Li+6 Hi+6 Proposed LSTFE Back-End Architecture Low Comparator Leading-Edge-Enable Domain 8:1 Multi-plexing (clock = 50 ns) FIFO (Leading and trailing transitions) Event Time Clock Period  = 400 nsec

  26. DIGITAL ARCHITECTURE VERIFICATION ModelSim package permits realistic simulation of FPGA code (for now, up to signal propagation delay) Simulate detector background and noise rates for 500 GeV running, as a function of read-out threshold. Per 128 channel chip ~ 7 kbit per spill  35 kbit/second For entire long shaping-time tracker ~ 0.5 GHz data rate (x100 data rate suppression) Nominal Readout Threshold

  27. LONG LADDER CONSTRUCTION

  28. OVERALL SUMMARY • Linear Collider R&D at SCIPP is: • Directly benefiting from SCIPP expertise • Focused on central issues for the ILC • Supporting leadership roles (international cooperation, oversight of tracking RD) • Creating synergies with other SCIPP programs • Providing key educational opportunities, undergrad through postdoc, with a good placement record

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