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Buffer Issues of Hardware synthesis from SDF graph

Buffer Issues of Hardware synthesis from SDF graph. CAP SNU Hoeseok Yang 2003. 8. 7. Contents. Buffering in SDF General Buffer Optimization Technique Buffer Minimization in Software Buffering Issues on Hardware Concurrency Resource sharing Buffer management in PeaCE VHDL domain

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Buffer Issues of Hardware synthesis from SDF graph

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  1. Buffer Issues of Hardware synthesis from SDF graph CAP SNU Hoeseok Yang 2003. 8. 7.

  2. Contents • Buffering in SDF • General Buffer Optimization Technique • Buffer Minimization in Software • Buffering Issues on Hardware • Concurrency • Resource sharing • Buffer management in PeaCE VHDL domain • Future Works

  3. Buffering in SDF • Optimal Buffer Size is determined by schedule. • Once schedule is determined, we can obtain optimal buffer size statically. • Then, how can we get a good schedule? • How can we manage the trade-off relationship btw timing and area in VHDL domain.

  4. 3 2 1 1 A B C 2 Maximum buffer size in eAB 8 3 4 Buffering in SDF • S1 ; AABBBCCC • S2 ; BCABCABC • S3 ; ABBCCABC

  5. General Buffer Optimization Technique • Most conservative way- Nothing is shared • dedicate #TNSE buffers for each arc • Edge optimized- optimize SDF ‘arc by arc’ • Globally optimized- optimize SDF globally

  6. General Buffer Optimization Technique • Most conservative way • Edge optimized • Globally optimized

  7. 3 2 1 1 A B C 2 Buffer Minimization in Software Repetition count qA:qB:qC = 2:3:3 In Conservative way, This can be valid in any schedule.(Schedule Independent Buffering)

  8. Buffer Minimization in Software • In Edge optimized situation,- AABBBCCC- BCABCABC

  9. Buffer Minimization in Software • In Globally optimized situation,- AABBBCCC- BCABCABC

  10. 2 3 2 1 A B C 10 20 10 A2 C3 A1 C4 C2 B1 B2 C1 A3 Buffering Issues on Hardware • Concurrency management Repetition count qA:qB:qC = 3:2:4

  11. Relatively, easy to control! A1 C1 A2 A3 C2 C3 C4 B1 B2 0, 10, 20 20, 40 40, 50, 60, 70 B C A 3 3 3 2 2 2 “0”->”1”20 40 “0”->”1”->”0”->”1” 40 50 60 70 “10”->”01”->”10”->”01” 70 80 90 100 “100”->”010”->”001” 0 10 20 Buffering Issues on Hardware Without parallelism, No buffer sharing.

  12. Relatively,Hard to control and many control signal needed A1 C1 A2 A3 C2 C3 C4 B2 B1 0, 10, 60 20, 70 40, 50, 90, 100 A B C “0”->”1”->”0”->”1”40 50 90 100 “000”->”111” 20 70 “1100”->”0011”->”1100” 0 10 60 Buffering Issues on Hardware Without parallelism, arc buffer sharing.

  13. Relatively,Hard to control and many control signal needed A1 C1 A2 A3 C2 C3 C4 B2 B1 0, 10, 20 20, 40 40, 50, 60, 70 A B C “0”->”1”->”0”->”1”40 50 60 70 “000”->”111” 20 40 “1100”->”0011”->”1100” 0 10 20 Buffering Issues on Hardware With parallelism, arc buffer sharing.

  14. C4 A1 C1 A2 A3 C2 C3 B2 B1 C B A B C A How many multiplexors and control signals do we need to synthesis this hardware? Buffering Issues on Hardware With parallelism, arc buffer sharing and multiple resources.

  15. Buffering Issues on Hardware • Resource Sharing

  16. disaster… Buffering Issues on Hardware • And then… • Delay(initial tokens) • Pipeline • Loop • Global buffer optimization • Etc…

  17. Buffer Management in PeaCE VHDL domain • Supports FRDF • Supports Resource Sharing • Use conservative buffer policy • Minimize buffers in loop

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