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Chapter 2:

Chapter 2:. 22444 - Computer Architecture & Organization (1). Instructions: Language of the Computer. Basic Computer Organization. The 5 Classic Components of a Computer The Basic Hardware/Software Interface The Stored-Program Concept. Instructions. Assembly Language Instruction:

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Chapter 2:

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  1. Chapter 2: 22444 - Computer Architecture & Organization (1) Instructions: Language of the Computer

  2. Basic Computer Organization • The 5 Classic Components of a Computer • The Basic Hardware/Software Interface • The Stored-Program Concept

  3. Instructions • Assembly Language Instruction: Perform: a = b + c ADD a, b, c ; a  b + c What are ‘a’, ‘b’ and ‘c’? • The storage concept: • Registers (R1, R2 …) • Memory • Sequence of Instructions: Perform: a = (b + c) – (d + e)

  4. Memory Operands • Data Transfer Instructions • Memory Address (Location) • Slower than registers • Lower bandwidth than registers • Load and Store Instructions Memory 0 1 2 • •

  5. Constant Operands • Memory Operand Performa = b + 4 • Immediate Operand Memory b 4 • • 21 22 • •

  6. Memory Access • Height and Width 1 KB 4 KB • Address & Data 16 Locations  1 K Locations  1 M Locations  • Read & Write 8 bit Memory 4 3 0 1 • • 21 22 • • 1024 1 KB

  7. Opcode Operands Stored Program Architecture Memory 1024 x 32 Instructions (Program) Operands (Data) Binary Operand

  8. Memory Organization • Byte Access • Word Access • • 20 Byte 21 Byte • • • • 20 Byte Byte Byte Byte 24 Byte Byte Byte Byte • • • • 20 Byte Byte 22 Byte Byte • •

  9. Memory Organization • Mixed Access • Little Endian • Odd/EvenAlignment • • 20 Byte Byte 22 Byte Byte • • MSB DATA BUS LSB

  10. Memory Organization • Mixed Access • Alignment! • • 20 Byte Byte Byte Byte 24 Byte Byte Byte Byte • • MSB DATA BUS LSB

  11. Opcode Operands Instruction Representation • Instruction Format • Machine Language & Machine Code Sequence of instructions AssemblyLanguage ADD R1, R2, 47 5 1 2 2F 0101 0001 0010 00101111 5 1 2 2 F MachineLanguage

  12. Operations (Opcodes) • Arithmetic • Add, Sub, Mul, Div, Inc, Dec … • Logic • Shift • Logical & Arithmetic • Right & Left • Bitwise AND, OR, XOR • Complement (NOT) 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1

  13. Operations (Opcodes) • Shift Operation for Multiplication • Multiply by 2 • Shift Left 1 bit • Unsigned Binary • 2’s Complement • Multiply by 10 • BCD • Shift Left 4 bits 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1

  14. Control Instructions • Making Decisions (Conditional Branches) Performif (i == j) then a = b + c else a = b – c i == j ? a = b + c a = b – c

  15. Control Instructions • Transferring Execution • Unconditional Branch or Jump • Call Subroutine • Software Interrupt • • • • • • • • • • • • • •

  16. RISC & CISC • Reduced Instruction Set Computer • 32-Bit Storage: • Registers (R1, R2 … R31) • Memory • Arithmetic operations: • Simple • Limited to registers • Complicated Instruction Set Computer • IA-32

  17. Intel Architecture IA-32 • General-Purpose Registers (GPRs) • Segment Registers Segmented Memory Addressing(Real Mode) Also: “Accumulator” EAX AX AL “Base” EDI ESI ECX EDX EAX EBX DX CX DI AX BX SI AL CL BL DL “Count” “Division” “String Source” “String Destination” CS SS DS

  18. Intel Architecture IA-32 • Variable Length Instruction Format

  19. Intel Architecture IA-32

  20. Chapter 2 The End

  21. Chapter 2 Exercise 1 • Write an assembly language program to perform a+2b where ‘a’ and ‘b’ are stored in R1 and R2. • Write an assembly language program to swap two locations at memory addresses 10 and 20. • Rewrite the following program to run faster:SUB R1, R1, R1INC R1ADD R2, R3, R1 • A memory has 4 bits of address and 4 bits of data. Determine the total number of bits inside it.

  22. Chapter 2 Exercise 2 • Determine the value of R1:LD R1, M [ 43 ] • Write the assemblyinstruction at 44. • Assuming 8-bit registers, determine the value of R1:Load Immediate R1, Binary ‘11110010’Arith Shift Right R1 • Assuming iandjare integers,R1= i and R2 = j, write the C-language statement for:Compare R1, R2 Jump Equal Label_1 Clear R1Label_1: Clear R2

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