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Lecture 6

ITEC 1000 “Introduction to Information Technology”. Lecture 6. The CPU and Memory. Lecture Template:. CPU Registers Register operations Memory implementation Computer Buses Instructions Using the Stacks Multiple Data Instructions. Computer unit. CPU. Highest Address Memory Lowest

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Lecture 6

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  1. ITEC 1000 “Introduction to Information Technology” Lecture 6 The CPU and Memory

  2. Lecture Template: • CPU • Registers • Register operations • Memory implementation • Computer Buses • Instructions • Using the Stacks • Multiple Data Instructions

  3. Computer unit CPU Highest Address Memory Lowest Address ALU Input/outputinterface Control unit Program counter • Memory is separate from the CPU

  4. Components of the CPU (1 of 2) • ALU (arithmetic logic unit) • Performs arithmetic and logic operations (data changed) • Arithmetic: add, subtract, multiply, divide, etc. • Logic: AND, OR, NOT, Shift, etc. • Data held temporary • CU (control unit): functions • performs fetch/execute cycle • Accesses and retrieves program instructions from the memory and issues commands to the ALU • Moves data to and from CPU registers and other hardware components (no change in data) • Registers • Example: Program counter(PC) or instruction pointer determines next instruction for execution

  5. Components of the CU (2 of 2) • Program counter (instruction pointer) • Contains the address of the current or next instruction • Normally instructions are executed sequentially • Memory management unit • Supervises fetching of instructions and data from memory • I/O Interface • Provides mechanism for input/output of data • sometimes combined with memory management unit in a single Bus Interface Unit

  6. Concept of Registers • Single storage locations within the CPU used for a particular purpose • Used to hold a binary value temporarily • Manipulated directly by the Control Unit • Each register is wired within the CPU directly (no address needed) for specificfunction • Size in bits or bytes (not MB like memory) • Can hold data, an address or an instruction

  7. Registers: what they do • Hold data being processed • Hold instruction being executed • Memory or I/O address being accessed • Keep status of the computer • Conditional branch instructions

  8. General-Purpose Registers • User-visible registers • Part of ALU • Accumulators • Typically several dozen in modern CPUs (R0, R1,…) • Hold data of arithmetic operations • Hold intermediate results or data values, e.g., loop counters • To transfer data between different memory locations and between I/0 and memory

  9. Special-Purpose Registers • Part of CU • Program Counter Register (PC) (instruction pointer) • Holds address of the currently executed instruction • Instruction Register (IR) • Holds the actual instruction being executed • Memory Address Register (MAR) • Holds the address of a memory location • Memory Data Register (MDR) • Holds the actual data value from location specified in MAR • Flags (one-bit register) to track special conditions like arithmetic carry and overflow, power failure, internal computer error • Status Registers • Several flag registers grouped together

  10. Register Operations • Load values from other locations (registers and memory) • Destroys (erases) previous value in destination • Source register (or memory location) unchangeable • Addition and subtraction • Result stored in the register • Shift or rotate (left or right) data • Test contents for conditions • zero • Positive/negative • To large

  11. Program Counter ( PC ) A dedicated register in the CPU Contains the address in memory of the current instruction being executed. Incremented automatically after each instruction. May be forced to change: e.g. “jump” instruction. Usually initialized to zero when machine starts, or is reset.

  12. Instruction Register ( IR ) A dedicated register in the CPU which contains the actual current instruction. Op Code + Address What To Do Location of Data 1101 101101100100 Simple 16-bit example:

  13. Accumulator A dedicated register (or set of registers) in the CPU used for the actual manipulation of data Default source (or destination) register Usually contains results of arithmetic or logical operations

  14. Operation of Memory • Each memory location has a unique address • Address from an instruction is copied to the MAR which finds the location in memory • CPU determines if it is a store or retrieval • Transfer takes place between the MDR and memory • MDR is a two way register

  15. MAR and MDR Memory Address Register (MAR) Contains Address in memory to find or place data Memory Data Register (MDR) Contains Actual Data to be placed in location given in MAR, or which has been retrieved from location given in MAR

  16. Generic CPU With Registers Program Counter ( PC ) Memory Instruction Register ( IR ) Memory Address Register ( MAR ) Memory Data Register ( MDR ) Accumulator ( A or Acc )

  17. Data Address MAR, MDR and Memory

  18. MAR-MDR: Example

  19. Individual Memory Cell

  20. Memory Capacity • Determined by two factors 1. Number of bits in the MAR • 2K where K = width of the MAR register in bits • 4 bits allow 16 locations • 8 bits allow 256 locations • 32 bits allow 4,294,967,296 or 4 GB 2. Size of each memory location, m • Memory capacity is the product: • m x 2K • Typical values: • k: 16, 17, 18, 19, 20, 21, 22, etc. • m: 8, 16, 32, 64

  21. Memory Implementation • Magnetic core (1949/51 – late 1960s/early 1970s • Random Access Memory (RAM) • Read Only Memory (ROM) • EEPROM • Flash ROM • Volatile • Nonvolatile

  22. RAM: Random Access Memory • Random – any piece of data can be accessed in a constant time regardless of physical location (unlike tapes, magnetic or optical discs) • Difference – in technical design • DRAM (Dynamic RAM) • Most common, cheap • Volatile: must be refreshed (recharged with power) 1000’s of times each second • SRAM (static RAM) • Faster to access than DRAM and more expensive than DRAM • Volatile • small amount used in cache memory for high-speed access

  23. RAM: Sample DRAM modules used as primary memory in PCs, workstations, servers.

  24. ROM - Read Only Memory • Implemented in early stored-program computers (e.g., ENIAC, after 1948) • If write protected, becomes read-only memory • Non-volatile memory • to hold built-in software that is not expected to change over the life of the computer (e.g., initial program that runs computer) • BIOS: initial boot instructions and diagnostics • Data are physically encoded into chips • EEPROM • Electrically Erasable Programmable ROM • Can be erased and reprogrammed, 1 byte at a time (up to 1000 times) • Slower and less flexible than Flash ROM • Flash ROM • Modern type of EEPROM (invented in 1984), faster (erase and write in blocks of bytes) • Higher endurance (up to 1,000,000 cycles) • E.g., USB Flash Drives

  25. ROM: Sample First erasable ROM, Intel 1702; erase window – in the middle

  26. Memory Maps • The usage of memory space on a system is commonly depicted in a “memory map” • The height of the map is determined by the number of addresses • The width of the map is usually 8 bits • E.g., • a system with a capacity of 216 bytes…

  27. Memory Map: Sample 1 7 6 5 4 3 2 1 0 FFFF 0002 0001 0000 Data bitposition The “bottom” of memory Hexadecimaladdress

  28. Use of Memory Maps • Memory maps are usually drawn to show “what is where” on a system • “what” can be: • RAM, ROM, I/O, empty space • “Where”: • Determined by the starting/ending addresses for each “block” of RAM, ROM, I/O,…, • E.g., • a memory map for a system with a capacity of 224 bytes with two 1 MB RAM modules residing consecutively at the bottom of memory….

  29. Memory Map: Sample 2 FFFFFF 200000 1FFFFF 100000 0FFFFF 000000 14 MB empty 224 bytes = 16 MB “capacity” 1 MB RAM 1 MB RAM

  30. Memory Space: Exercise 1 Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.) A: ? Skip answer Answer

  31. Memory Space: Exercise 1 Answer Q: A system with a memory capacity of 128 GB has four 32 MB memory modules installed. The rest of the memory is unused. How much memory space is available for future expansion? (Give your answer in decimal in megabytes.) A: 128 GB – 4 x 32 MB = 27 x 210 MB - 22 x 25 MB = (217 – 27) MB = (131,072 – 128) MB = 130,944 MB 210 = 127.875 GB

  32. Memory Space: Exercise 2 • Draw a memory map for a system with a capacity of 2 GB. Assume the system has three 32 MB memory modules residing consecutively at the bottom of memory. Illustrate the size of each block in MB and the starting and ending address of each block of memory in hexadecimal. Skip answer Answer

  33. Memory Space: Exercise 2 Answer 7FFFFFFF 06000000 05FFFFFF 04000000 03FFFFFF 02000000 01FFFFFF 00000000 1,952 MB empty 231 bytes = 2 GB “capacity” 32 MB RAM 32 MB RAM Note:2 GB = 2,048 MB 32 MB RAM

  34. Fetch-Execute Cycle • Two-step process because both instructions and data are in memory • Fetch • Decode or find instruction, load the code of the instruction from memory • Execute • Performs operation that instruction requires • Move/transform data

  35. Fetch-part of the Cycle • The value in the PC (program counter) register is the address of the memory location that holds instruction to be executed • First step is always: transfer (copy) the value in the PC to the MAR • Then computer can retrieve the instruction located at that address and place it in the MDR • PCMAR(step 1) • MemoryMDR • Next step: transfer instruction to the IR • MDR IR (step 2) • Remaining steps – instruction dependent

  36. Load Instruction • Next step: the address part of the instruction located in the IR is copied and placed in the MAR • Computer retrieves actual data located at the address in memory and places it in the MDR • IR [address]MAR(step 3) • MemoryMDR • Next step: MDR copies data to the “accumulator” register • MDR A (step 4) • Last step: PC is incremented • PC + 1PC(step 5)

  37. Load Accumulator: Sample (1 of 12) Task: Simple Eight bit system. Thirty-two memory locations (0 to 31). “Load” instruction is 010. Value in location 15 is ten (i.e.: binary 00001010) PC is at 5, about to increment. The instruction, 01001111, is in location 6.

  38. Load Accumulator: Sample (2 of 12) CPU Before PC increments Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00101 IR: (previous) MAR: (previous) MDR: (previous) A: (previous)

  39. Load Accumulator: Sample (3 of 12) Increment PC: PC = PC + 1 Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: (previous) MAR: (previous) MDR: (previous) A: (previous)

  40. Load Accumulator: Sample (4 of 12) MAR loaded with PC: PC -> MAR Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: (previous) MAR: 00110 MDR: (previous) A: (previous)

  41. Load Accumulator: Sample (5 of 12) Memory Location 00110 Accessed and Contents Placed in MDR: Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: (previous) MAR: 00110 MDR: (previous) A: (previous)

  42. Load Accumulator: Sample (6 of 12) Memory Location 00110 Accessed and Contents Placed in MDR: Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: (previous) MAR: 00110 MDR: 01001111 A: (previous)

  43. Load Accumulator: Sample (7 of 12) MDR copied to IR: MDR -> IR Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 00110 MDR: 01001111 A: (previous)

  44. Load Accumulator: Sample (8 of 12) IR [ address part ] -> MAR Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 01111 MDR: 01001111 A: (previous)

  45. Load Accumulator: Sample (9 of 12) Location in MAR (01111) Accessed Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 01111 MDR: 01001111 A: (previous)

  46. Load Accumulator: Sample (10 of 12) Contents of 01111 loaded into MDR Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 01111 MDR: 00001010 A: (previous)

  47. Load Accumulator: Sample (11 of 12) IR [op code] executed: MDR -> A Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 01111 MDR: 00001010 A: 00001010

  48. Load Accumulator: Sample (12 of 12) Finished ! Memory Location 31 15: 00001010 06: 01001111 Location 0 PC: 00110 IR: 01001111 MAR: 01111 MDR: 00001010 A: 00001010

  49. Load Fetch/Execute Cycle

  50. Store Fetch/Execute Cycle (1 of 2)

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