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Logic Design Lab3

Logic Design Lab3. 老師 : 伍紹勳 助教 : 江長庭 鄭仲傑. Equipment. IC ： 7408(AND) x 1 7432(OR) x 1 7486(XOR) x 1 LED x 3. x. Carry (C). y. Sum (S). x y C S. x. x. S. y. y. 1 1 1 0. y. C. x. Half Adder (HA). x + y C S. Half Adder.

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Logic Design Lab3

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  1. Logic Design Lab3 老師:伍紹勳 助教:江長庭 鄭仲傑

  2. Equipment • IC： • 7408(AND) x 1 • 7432(OR) x 1 • 7486(XOR) x 1 • LED x 3

  3. x Carry (C) y Sum (S) x y C S x x S y y 1 1 1 0 y C x Half Adder (HA) x + y C S Half Adder • Sum of Products : S = x’y + x y’= x  y C = x y 0 0 0 0 0 1 0 1 1 0 0 1

  4. Why do we need Full Adder (FA) ? • 1-bit addition ex: 1+1=10 Using HA is OK! • 2-bits addition HA is not enough!!! 1 1 1 + 1 1 We need a input Carry-in 1 1 0

  5. x S y Cn Cn+1 x y Cn Cn+1 S 1 1 1 1 1 Full Adder x y + Cn Cn+1 S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 • S = x y’Cn’ + x’y’Cn + x yCn + x’yCn’ = x  y  Cn Cn+1 = x y + xCn + yCn=x y + Cn (x  y ) 1 0 1 1 0 1 1 0 1 0

  6. x s y Cn Cn+1 Full Adder (FA) So many logic gates!!!

  7. Half Adder x S S Cn Half Adder x x S y C y y C x y S Cn Cn+1 HA + HA = FA x  y Cn (x  y ) Cn+1 =x y + Cn (x  y ) x y Less logic gates!!!

  8. Requirement • Choose HA + HA = FA • Requirement 1: 1-bit addition HA or FA (one input is zero) • Requirement 2: 2-bits addition HA + FA or FA + FA FA HA 1 1 1 +1 1 1 1 0 Waste!!! Not recommend

  9. x2 y2 S2 x Cn x1 S1 y1 y y Cn+1 (S3) C x 2-bits addition ( HA + FA ) x2 x1 + y2 y1 S3 S2 S1

  10. Debug method 1.Check有無接VCC跟GND 2.Check half adder 的值是否與真值表相同 3.Check full adder 的值是否與真值表相同 4.Check HA 與 FA 之間的連線是否正確

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