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This paper discusses techniques for reducing power consumption in microprocessor architectures by leveraging dynamic critical path information. Specifically, it categorizes instructions based on criticality—blue indicating critical and yellow non-critical. Various metrics are proposed, such as QOLD and QOLDDEP, to assess instruction criticality. The paper also highlights the implications of slow functional units and provides strategies for managing power consumption through circuit design and architecture adjustments. Overall, it emphasizes a criticality predictor's role in enhancing performance and reducing power usage.
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CS 7810 Lecture 14 Reducing Power with Dynamic Critical Path Information J.S. Seng, E.S. Tune, D.M. Tullsen Proceedings of MICRO-34 December 2001
Instruction Criticality • Blue instructions are critical • Yellow instructions are non-critical • -- they can be slowed without • increasing execution time • The critical path can change • Critical instructions are usually • executed in order
Criticality Metrics • QOLD – instructions that are the oldest in the • issueq are considered critical • can be extended to oldest-N • does not need a predictor
Criticality Metrics • QOLD – instructions that are the oldest in the • issueq are considered critical • can be extended to oldest-N • does not need a predictor • young instrs are possibly on mispredicted paths • young instruction latencies can be tolerated • older instrs are possibly holding up the window • older instructions have more dependents in the pipeline than younger instrs • This paper uses a predictor because early criticality info is required
Other Metrics • QOLDDEP: Producing instructions for oldest in q • ALOLD: Oldest instr in ROB • FREED-N: Instr completion frees up at least N • dependent instrs • Wake-Up: Instr completion triggers a chain of • wake-up operations • Instruction types: cache misses, branch mpreds, • and instructions that feed them
Slow FUs Slow units have twice the latency of fast units
Low Power Techniques • Slower circuit styles that consume less power • Smaller transistors consume less power, but take • longer to charge their load • Higher threshold voltage reduces leakage and • increases delay • Assumption: Leakage accounts for 10% of the • base; low power FUs consume 20% less dynamic • power and 50% less leakage
IPC to FU-Power Ratio • Approximates hot-spot evaluation • Number of thermal emergencies might be a better metric • Total-IPC/Total-Power is more suitable for ___ ?
Proposed Microarchitecture Criticality Predictor In-order issueq FUs Dispatch o-o-o issueq FUs FUs FUs FUs FUs • Imbalance between the two queues can worsen performance • Favorable implications for temperature • o-o-o issueq can have long latency • Criticality predictor is likely to not be a hot spot
Power-Aware Architectures • Speculation control • Criticality • Leakage control by de-activating structures • Dynamic voltage and frequency scaling • Metrics: temperature, peak power, battery life, • packaging costs, power delivery, etc.
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