1. Digital Processing System Shuvra S. BhattacharyyaDepartment of Electrical and Computer Engineering, andInstitute for Advanced Computer Studies University of MarylandCollege Park MD 20742ssb@eng.umd.edu, (301)405-3638,http://www.ece.umd.edu/~ssb/ With Neil Goldsman and Babis Papadopoulis Laboratory affilations: Digital Signal Processing Laboratory, VLSI Design Automation Laboratory, Embedded Systems Research Laboratory, Communications and Signal Processing Laboratory

2. Digital Processing Platform • Low power micro-controller • Small size for compact integration • Enables adaptation of node behavior with changing requirements, environmental characteristics, and network state • Enables experimentation with different algorithms and protocols • Enables use of energy saving processor modes and associated operating system functionality • Development of streamlined software implementations • Highly memory-constrained software implementations are required due to size and energy constraints • Leverage our previous work in synthesis of memory-efficient embedded software implementations • Employ formal programming models, and apply graph-theoretic analysis and optimization of program structure • Explore migration into ASIC or 3D-integrated system

3. Low power sleep mode Check for new data Fuse with prior data Example of Software Structure Receiver No new data Periodic wake-up Sensor Transmitter No Broadcast new data Extract data Yes Need to update neighbors?

4. Protocol Set-up and System Configuration • Handshaking • Source channel coding • Integrate with transceiver to establish PLL timing • Establish error correction coding • Establish low-complexity decoding • Assign transmission power • Assign processing tasks to network nodes

5. System-level Optimization Example:Task Assignment Algorithms • Need to balance communication and computation throughout the network • Develop models of power consumption in network nodes and communication links • Develop task graph models of overall network functionality • Develop algorithms to embed task graph algorithm specifications into the network • Assign processing tasks to network nodes • Turn off idle nodes • Large design space • Explore evolutionary algorithms to optimize task graph embeddings

6. Selection Phenotype space(Original search space) P(t) P(t+1) G(t+1) Evolutionary Algorithms Decoding function Genetic operators Genotype space(Genetic representation) G(t)

7. References: selected prior work related to embedded software optimization • N. K. Bambha, S. S. Bhattacharyya, J. Teich, and E. Zitzler. Systematic integration of parameterized local search in evolutionary algorithms. IEEE Transactions on Evolutionary Computation. To appear. • S. S. Bhattacharyya. Hardware/software co-synthesis of DSP systems. In Y. H. Hu, editor, Programmable Digital Signal Processors: Architecture, Programming, and Applications, pages 333-378. Marcel Dekker, Inc., 2002. • P. K. Murthy and S. S. Bhattacharyya. Shared buffer implementations of signal processing systems using lifetime analysis techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(2):177-198, February 2001. • S. S. Bhattacharyya, R. Leupers, and P. Marwedel. Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems --- II: Analog and Digital Signal Processing, 47(9):849-875, September 2000.