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Designing with Quartus

Designing with Quartus. Quartus Development System Feature Overview. Quartus Development System. Quartus Development System features: Fully integrated design entry, processing, and verification tools: Multiple design entry methods Logic synthesis Place & route Simulation Timing analysis

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Designing with Quartus

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  1. Designing with Quartus

  2. Quartus Development System Feature Overview

  3. Quartus Development System • Quartus Development System features: • Fully integrated design entry, processing, and verification tools: • Multiple design entry methods • Logic synthesis • Place & route • Simulation • Timing analysis • Device programming • NativeLink • Revision Control Interface • Intellectual Property (IP) Support • SignalTap • Extensive On-Line Help

  4. More Features • Incremental Recompilation • Internet-enabled technical support • Supports multiple platforms1 • Quartus runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations • Extensive on-line help • Network licensing supported on both Windows-based PCs and Unix-based workstations Note 1: Please refer to Quartus’ ReadMe file to determine which version of the Operating System is supported for each platform

  5. Quartus Operating Environment Project Navigator Window Status Window Messages Window

  6. QuartusDesign Methodology

  7. Design Entry Design Modification Design Specification Design Compilation Functional Verification Command-LineMode:Scripting Timing Verification Device Programming In-System Verification System Production

  8. Design Methodologies • Quartus supports three common design methodologies: • Top-down • Create a top-level of the design first, and then break down the design into lower-level design blocks. • Bottom-up • Begin by creating the lower-level design blocks first and then stitch together the design at the top-level. • Middle-out • Start in-between Top-down and Bottom-up design methodologies

  9. Design Entry • Multiple design entry methods • Quartus • Block/Schematic Editor • Text Editor • AHDL, VHDL, Verilog • Memory Editor • Hex, Mif • Third party EDA tools • EDIF • HDL • VQM • Add flexibility and optimization to the design entry process by: • Mixing and matching design files • Using LPM and Megafunctions to accelerate design entry

  10. Design Entry Files Verilog VHDL Quartus Block Editor AHDL Schematic Top-Level File .bdf .gdf .bsf .edf .edif .tdf .vhd .v Text File Schematic Quartus Text Editor Quartus Memory Editor MegaWizard Manager Exemplar, Synopsys, Synplicity, etc... Top-level design files can be .bdf, .tdf, .vhd, .vhdl, .v, .vlg, .edif or .edf .v, .vlg, .vhd, .vhdl, vqm Text File Block File Symbol File Text File Text File Text File Generated within Quartus Imported from third-party EDA tools

  11. Resource Libraries • The following libraries are added to the project by default • LPM • Library of Parameterized Modules ( LPMs ) • Industry standard logic functions • LPM_ADD_SUB, LPM_COUNTER, etc. • Others • 7400 series logic functions (to provide support for older designs) • Other legacy functions like 161mux, 8fadd, etc. • Primitives • Basic logic building blocks

  12. Add User Libraries Menu Bar: Project > General Setting... Step 1: Select User Libraries Step 2: Select Library path Step 3: Click Add Step 4: Click OK Adding User Libraries can also be done using Project Wizard. Refer to the section on Project Wizard for more information

  13. Text Design Entry • Available Features • Line numbering in the HDL text files • Preview of HDL templates • Syntax Coloring • When editing a text file, an asterisk (*) appears next to the filename • After saving the file, the asterisk disappears • Enter text description • AHDL (.tdf) • VHDL (.vhd) • Verilog (.v)

  14. HDL Templates Select HDL language. Select Template section. Preview window display section Menu Bar: Insert > Template… or click on the shortcut button

  15. Edit Options Upper Left-hand Corner of the Screen Increase Indent Decrease Indent Find Matching Delimiter Upper Left-hand Corner of the Screen

  16. Text Editor: Options Menu Bar: Tools > Options...

  17. AHDL • Altera Hardware Description Language • High-level hardware behavior description language • Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. • Can create AHDL Design File (.tdf) with the Quartus text editor or any standard text editor and compile it directly with Quartus • Text editor has AHDL templates and syntax coloring

  18. Verilog • 1993 Verilog IEEE 1364 standard Hardware Description Language • Can create Verilog design files with the Quartus text editor or any standard text editor and compile it directly with Quartus • Text editor has Verilog templates and syntax coloring • Features • Tasks • 2-D Arrays • Empty placeholder • State machine recognition • Verilog TestBench support Learn more about Verilog in Altera Verilog Customer Training Classes

  19. VHDL • VHSIC Hardware Description Language • 1987 and 1993 IEEE 1074 standards supported • Can create VHDL design files (.vhd) with the Quartus text editor or any standard text editor and compile it directly with Quartus • Text editor has VHDL Templates and syntax coloring • VHDL TestBench support Learn more about VHDL in Altera VHDL Customer Training Classes

  20. Block Diagram/Schematic File Editor This is both a block diagram editor and a schematic file editor • Block diagram entry is mainly for top-down design methodology • Schematic file entry is the traditional schematic design entry • User can enter blocks, primitives, LPMs, and megafunctions from Quartus-provided or user libraries • Provides “smart” block connection and mapping

  21. Block Editor - Entry Process • Create new block design file • Draw block diagram or enter design components (symbols) • Enter port and parameter information • Connect components with connectors (wires, buses & conduits) • Add mapping properties to conduits, if needed • Save the design • The file extension is .bdf • Generate HDL/graphic file for the lower-level blocks • Create symbol or include file of the top-level block design

  22. Block Editor - Create New File • Create a block/schematic file Menu Bar: File > New > Block/Schematic document Open new file Select Block/Schematic Document

  23. Block Editor - Enter Symbols • Enter symbols from libraries - LPMs, primitives, others Click on the toolbar option “Insert Symbol” OR Double-click in block editor to insert symbols Symbol libraries Preview the Symbol

  24. Block Editor - Draw Block • Create block using the toolbar and enter ports Click on the toolbar option “Block” to draw a block diagram Block A Right-click on the block. Select Properties from the pop-up menu. Enter port information.

  25. Block Editor - Make Connections • Wire (Single bit line) • Bus (Multiple bits) • Conduit • Connects blocks to any other objects Wire Bus

  26. Block Editor - Check Conduit Connections Right Mouse Click on the connector > Conduit Properties

  27. Block Editor - “Smart” Connections • Quartus has “smart” block connecting and mapping • Unnecessary to label conduits if the I/O names between different blocks are the same • One conduit will connect all the common I/Os between the blocks Mapper Connector Block A Block B

  28. Block Editor - Conduit Properties • Map the block I/Os when the I/O names are different between the blocks 1 First, label the connector • Select connector  right-click  choose Properties  enter Name Block A Block B ConnectorAB ConnectorAB Enter Signal

  29. Mapper Properties Double-click on the mapper Block B ConnectorAB 2 Select the mapper and double-click on it to open the Mapper Properties dialog box 3 In the General tab, set the Mapper Type - Input, Output, Bidir 4 In the Mappings tab, set the I/O on block and connector signal 5 Click Add and hit OK Block A

  30. Block Editor - Make Connections 6Enter mapper properties on both the blocks 7 Now, the I/Os are connected Mapper Annotation Box Block A Block B ConnectorAB IIIII

  31. Block Editor - Save Design • Save the design file with .bdf extension Block A ConnectorAB Block B Design File Name

  32. Block Editor - Generate Design File • Create HDL or graphic design file for individual blocks Block A Block B ConnectorAB Right-click on the symbol to open the pop-up menu Select Create Design File from the menu

  33. Block Editor - Generate Design File • Choose from the File Type and enter File Name Block A Block B ConnectorAB Select from AHDL, VHDL, Verilog or Graphic option

  34. Create Design File Quartus creates a design file that contains the port names that are specified in your block. These lines are necessary for Quartus to update the source code module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule

  35. Update Design File... After Before If you change the name or number of I/Os in your block, Quartus can update the design file for you Right mouse click Update Design File...

  36. Updated Design File module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2, out3 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; output out3; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule Quartus updated the source file with the additional pin, out3

  37. Block Editor - Designing Hierarchically? • Menu Bar: Tools > Create Symbol for Current File • Menu Bar: Tools > Create Include File for Current File Creates .bsf file Creates .inc file

  38. Block Editor - Options • Menu Bar: Tools > Options

  39. Memory Editor • Create or edit memory files in hex format (.hex) or memory initialization format (.mif) • For Design Entry • If you have a memory block in your design (ex. RAM, ROM, or Dual-port RAM), you can use the memory editor to create a memory initialization file to initialize your memory block • For Simulation • You can create an initialization file to initialize your memory during simulation

  40. Memory Editor - Create New File • Create memory file Menu Bar: File > New > Other Files tab Hex Document Mif Document

  41. Memory Editor - Create New File • Create memory file • Enter Number of Words and Word Size

  42. Memory Editor - Create New File • Opens memory editor window with the required number of words and word size Words OR Cells

  43. Memory Editor - Options • Changing some options of memory editor • View  Select from available options Show ASCII Equivalents Cell Per Row

  44. Memory Editor - Options • Changing radix settings of memory editor • View  Address/Memory Radix Address Radix Memory Radix

  45. Memory Editor - Edit Contents • Create memory file • Edit contents of the memory file Select the word and type in a value OR Select the word and right click to select an option from the pop-up menu

  46. Memory Editor - Save File • Create memory file • Save the memory file as .hex or .mif file .

  47. Memory Editor - Memory Size Wizard Need to Edit Memory Size Contents? • Quartus Provides the Memory Size Wizard • Edit Word Size • Edit Number of Words • Specify How to Handle Word Size Change • Increasing Word Size • Pad Words • Combine Words • Decreasing Word Size • Truncate Words From Left • Truncate Words From Right .

  48. Memory Editor - Memory Size Wizard 1.Open Memory File 2.Select the Memory Size Wizard

  49. Memory Editor - Memory Size Wizard • Decreasing Memory Size 16 bits To 8 bits 3a. How should Quartus handle excess bits? - Truncate MSBs - Truncate LSBs - Split Words/Increase Memory Depth

  50. Memory Editor - Memory Size Wizard • Increasing Memory Size 16 bits To 32 bits 3b. How should Quartus pad words? - Combine Words - Sign Extend (Signed) - Pad MSBs With Zeros (Unsigned)

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