Quartus II Schematic Design Tutorial for Cyclone Device

Quartus II Schematic Design Tutorial Xiangrong Ma max6@unlv.nevada.edu

Design Flow

Create Project • Project information • Directory • Project name • Top level name • Device • Select Cyclone • (small & fast for compile)

Design Capture • Create a new Schematic File • Add Gates • Add Pins • Check Design

Compile(Synthesis & Fit & STA) Fix Errors Check Reports

Create test stimulus file • Create a waveform vector File • Add input/output pins(using Node Finder) • Change value for input pins • Keep outputs as “X”

Setup Simulation Environment • Right Click on Project, • choose “Settings” • Select “Simulator Setting” • Select input file • Select Simulation mode • Functional • timing

Generate Netlist • Functional Simulation • Generate Functional netlist file for simulation • 0 delay, just “functional” • Timing Simulation • After Compilation, timing information was extracted from devices • Wire delay/logic delay information would be used for “back-annotated simulation” • Much more accurate

Run Simulation

Analysis S=A and B C=A or B Fix errors

File extension description .qpf Quatus Project File .qsf Quatus Setting File .vwf Vector Waveform File .bdf Block Design File .rpt Report

URLs • https://www.altera.com/download/quartus-ii-we/dnl-quartus_we-v72.jsp Quartus II 7.2 Web Edition(sp3)

Quartus II Schematic Design Tutorial for Cyclone Device

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