Accelerating Design Cycles Using Quartus II

1. Accelerating Design Cycles Using Quartus II SignalTap II Embedded Logic Analyzer

2. SignalTap II Agenda • SignalTap II Overview & Features • Using SignalTap II Interface • Advanced Triggering

3. SignalTap II ELA • Captures the Logic State of FPGA Internal Signals Using a Defined Clock Signal • Gives Designers Ability to Monitor Buried Signals • Connects to Quartus II through FPGA JTAG Pins • Captures Real-Time Data • Up to 200 Mhz • Is Available for Free • Installed with Full Subscription or Web Edition • Installed with Stand-Alone Programmer

4. SignalTap II Device Support • Stratix & Stratix II • Stratix GX • Cyclone & Cyclone II • Excalibur • Mercury • APEX II • APEX 20K/E/C

5. How Does It Work? • Configure ELA • Download ELA into FPGA along with Design • ELA Samples Internal Signals • Quartus II Communicates with ELA through JTAG

6. ELA Resource Utilization • ELA Uses Device Resources for Implementation • ALMs/LEs for ELA Megafunction & Routing • Memory for Sample Storage • LE Count Is a Function of the Number of Channels & Trigger Levels • Memory Block Count Is a Function of Number of Channels & Sample Depth • Selectable Trade-off Between Depth & Number of Channels • 128K Sample Depth with 1024 Channels Is Not Practical – 32,768 M4K Blocks

7. Stratix/Cyclone Sample Resource Usage

8. Modes of Operation • Three Different Configurations • Internal RAM ELA Configuration • Debug Port ELA Configuration • Hybrid Approach • Provides Flexibility Based on Available Device Resources • Memory Resources Are Limited • Use Debug Port Configuration • Pin Resources Are Limited • Use Internal RAM Configuration

9. Signals From Internal Nodes ELA Core Logic ELA Memory To JTAG Connector JTAG Port Internal RAM Configuration • Acquired Data Saved in Device Internal RAM • Streamed Off-device through JTAG Port • LEs Required to Implement ELA Core Logic

10. ELA Core Logic Signals From Internal Nodes Signals to Debug Ports To Unused I/O Pins Debug Port Configuration • Acquired Data Routed to Unused Device I/O Pins • Captured by External Logic Analyzer or Oscilloscope • LEs Required to Implement ELA Core Logic • I/O Pins Required for External Analysis

11. Supported Download Cables • USB Blaster • USB Port Cable • ByteBlaster™ II • Parallel Port Cable • ByteBlasterMV™ • Parallel Port • MasterBlaster™ • USB / Serial Port Cable

12. SignalTap II Key Features • Setup • Data Triggering • Data Capture • Data Analysis

13. Setup Data Triggering Data Capture Data Analysis Setup Features • Up to 1024 Data Channels • Multiple Analyzers in One Device • Supports Analysis of Multiple Clock Domains • Each Analyzer Can Run Simultaneously • Resource Usage Estimation • Incrementally Routes New Signals

14. Setup Data Triggering Data Capture Data Analysis Data Triggering Features • Up to 10 Trigger Levels Per Channel • Allows Application of Simple (Basic) & Complex (Advanced) Triggering Schemes • Defines a Sequential Pattern of Logic Conditions • Each Trigger Level is Logically ANDED • If (L1 & L2 ... & L10) == TRUE  Data Capture

15. Setup trigger Samples Captured Samples Captured Data Triggering Old Samples New Samples TIME Data Capture Data Analysis Data Triggering Features (Cont.) • Three Main Trigger Positions • Trigger Input • Setup External Trigger to Trigger the Analyzer • Trigger Output • Signifies Trigger Event Occurred with SignalTap II • Use One ELA’s Trigger Output as Trigger Input for Another Data Triggering

16. Setup Data Triggering Data Capture Data Analysis Data Capture Features • Up to 128K Samples Per Channel • Increases Chance of Catching Target Event • Two Methods of Data Acquisition • Circular • Segmented • Mnemonic Tables • Create User-Defined Labels for Bit Sequences (Ex. State Machine)

17. Setup Data Triggering Data Capture Data Analysis Data Analysis Features • Data Export • Save Real Time Data & Apply Data as Stimulus to Simulation • Data Log • Keep a a Log of Captured Data • Compare Old Data Vs. New Data

18. SignalTap II Agenda • SignalTap II Overview & Features • Using SignalTap II Interface • Advanced Triggering

19. SignalTap II Design Flow • Use SignalTap II File (.STP) • Use Quartus II GUI • STP Separate from Design Files • Use Quartus II MegaWizard • Instantiate Directly into HDL

20. Using STP File • Create .STP File • Assign Sample Clock • Specify Sample Depth • Assign Signals to STP File • Specify Triggering • Setup JTAG • Save .STP File & Compile with Design • Program Device • Acquire Data

21. 1) Creating a New .STP File • To Create a .STP File • Method 1 • Select the in Quartus II • Method 2 • Select New (File Menu) • OtherFiles • SignalTap IIFile • Default File Name Will Be STP1.stp

22. Main .STP File Components JTAG Chain Configuration .STP File Instance Manager Waveform Viewer Signal Configuration

23. Instance Manager • Instance Manager • Selects Current ELA to Setup/View • Displays the Current Status of each Instance • Displays Size (Resource Usage) of ELA

24. Signal Configuration • Manages Data Capture & Signal Configuration • Sample Clock • Sample Depth • Trigger Position • Trigger-In & Trigger-Out

25. Assign Sample Clock • Use Global Clock for Best Results • Data Written to Memory on Every Sample Clock Rising Edge • Clock Signal Cannot Be Monitored as Data • External Clock Pin Created Automatically if Clock Unassigned • auto_stp_external_clock • ELA Expects External Signal to be Connected to Clock Pin

26. Specify Sample Depth • Sample Depth • Set Number of Samples Stored for each Data Signal • 0 to 128K Sample Depth • 0 Selected When External Analyzer Is Used • Select RAM Type for Stratix & Stratix II Devices • Useful when Preserving a Specific Memory Type is Necessary

27. Data Capture • Circular • Specify Trigger Position • Pre • Center • Post • Continuous • Segmented • Specify Segment Depth

28. Circular Buffer • Data is Circled through the Acquisition Buffer until the Trigger Event Occurs • After the Trigger Event Occurs, Post-Trigger Data is Collected until the Buffer Fills up

29. Example: Circular Buffer

30. Segment 2 Segment 1 Segment 3 Trigger Event Segmented Buffer • Acquisition Buffer is Segmented into a Smaller, User Defined Blocks • Example: 4K is segmented into 4-1K segments • Data is Circled through the Acquisition Buffer until the Trigger Event Occurs • When the Trigger Event Occurs, Post-Trigger Data is Collected until the Segment Fills up • Process Repeats until all Segments are Filled

31. Example: Segmented Buffer

32. Triggering • Trigger Levels • Indicate up to 10 Trigger Conditions • Trigger-In • Any I/O Pin Can Trigger the SignalTap II Analyzer • Generates auto_stp_trigger_in_n Pin • Trigger-Out • Indicates When a Trigger Pattern Occurs • Generates auto_stp_trigger_out_n Pin • Delayed 4 Clock Cycles after Actual Trigger Event

33. Waveform Viewer • Setup Tab Describes the Signal Settings • Data Signals vs. Trigger Signals • Sets up Each Triggering Level (L1 – L10) • Data Tab Displays Captured Data

34. STP File Waveform Viewer Setup Tab Data Tab

35. Set up Waveform Viewer • Add Signals to Viewer Window • Use Node Finder • Main Menu, Toolbar, or Right-Click Click • Only Signals that Are Found Using the SignalTap II Filter in the Node Finder Can Be Captured • Important: Not All Signals Are Available • Data Enable Column Check Box Controls Whether Signal Is Captured As Data • Ex. Removing Reduces Sample Memory Size • Trigger Enable Column Check Box Controls Whether Signal Is Disregarded as a Trigger Pattern • Ex. Signal Used Only for Data Collection

36. Basic Triggering All Signals Must Be True for Level to Cause Data Capture Right-Click to Set Value

37. Debug Port • Routes Data Signals to Spare I/O Pins for Capture by External Logic Analyzer • Quartus II Automatically Generates auto_stp_debug_out_m_n Pin • m Represents the Instance Number of the Analyzer • n Represents the Order the Debug Port Pin Occurs in the Signal List

38. Mnemonic Table • Allows a Set of Bit Patterns to Be Assigned User-Defined Names • Right-Click in the Setup View of an STP File & Select Mnemonic Setup • Select Add Table • Select Add Entry • Ex. State Machines or Decoders/Encoders

39. JTAG Chain Configuration • Select Programming Hardware • Scan Chan Button Automatically Determines Devices Physically Connected to the Chain • Detects Non-Altera Devices & Displays Them as Unknown

40. 2) Save .STP File & Compile • SignalTap II Logic Analyzer Control in Compiler Settings • Assignments  Settings • Specify the STP File to Compile with Project

41. 3) Program Device(s) • Use Quartus II Programmer or STP File • Program Button in the SignalTap II Interface Only Configures the Selected Device in Chain • Use Quartus II Programmer to Program Multiple Devices • Can Create a STP File for each Device in the JTAG Chain

42. 4) Acquire Data • SignalTap II Toolbar & STP File Controls • Run • Autorun • Stop • Read Data (Reads in Data from Last Analysis)

43. Displaying Acquired Data Format in Time or Sample Number • Display Signal as Bar or Line Chart • Export to Other Tools for Viewing or Analysis (File Menu) • Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File

44. Using STP File Review • Create .STP File • Assign Sample Clock • Specify Sample Depth • Assign Signals to STP File • Specify Triggering • Setup JTAG • Save .STP File & Compile with Design • Program Device • Acquire Data

45. Using MegaWizard • Create Instantiation Using MegaWizard • Number of Data Channels • Sample Depth • Number of Triggers Inputs • Number of Trigger Levels (Advanced/Basic) • Instantiate into Design • Synthesize Design • Create STP File Based on Instances & Edit • Acquire Data

46. 1) Create Instantiation Size SignalTap II Instance Basic or Advanced Triggering?

47. 2 & 3) Instantiate & Synthesize

48. 4) Create STP File (File Menu) & Edit • Generates New STP File Based on Number Design Instances

49. Recompilation • Recompilation Required • Addition/Removal of Instance, Data or Trigger • Modifying the Sample Clock or Buffer Depth • Enabling/Modifying Trigger-In/Trigger-Out • Enabling the Debug Port • Lock Mode Prevents Changes Requiring Recompilation

50. Incremental Routing • Switches between Nodes without Full Recompilation • Maximizes Effectiveness