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Dynamic Hardware Branch Prediction

Dynamic Hardware Branch Prediction. Goal Allow the processor to resolve the outcome of a branch early, thus preventing control dependences from causing stalls. Branch-Prediction Buffer. Simplest Branch history table

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Dynamic Hardware Branch Prediction

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  1. Dynamic Hardware Branch Prediction • Goal • Allow the processor to resolve the outcome of a branch early, thus preventing control dependences from causing stalls. CSCE 614 Fall 2009

  2. Branch-Prediction Buffer • Simplest • Branch history table • Small memory indexed by the lower portion of the address of the branch instruction • 1 bit says whether the branch was taken or not. • If the bit turns out to be wrong, the prediction bit is inverted and stored back. CSCE 614 Fall 2009

  3. Example • Consider a loop branch whose behavior is taken nine times in a row, then not taken once. What is the prediction accuracy for this branch? Even if a branch is almost always taken, we predict incorrectly twice when it is not taken. CSCE 614 Fall 2009

  4. 2-bit Prediction Scheme • A prediction must miss twice before it is changed. CSCE 614 Fall 2009

  5. n-bit Saturating Counter • Values: 0 ~ 2n-1 • When the counter is greater than or equal to one-half of its maximum value, the branch is predicted as taken. Otherwise, not taken. • Studies have shown that the 2-bit predictors do almost do well, and thus most systems rely on 2-bit branch predictors. CSCE 614 Fall 2009

  6. 4096-entry 2-bit prediction buffer CSCE 614 Fall 2009

  7. CSCE 614 Fall 2009

  8. Correlating Branch Predictor • It may be possible to improve the accuracy if we look at the behavior of other branches. DSUBIU R3, R1, #2 BNEZ (b1) R3, L1 DADD R1, R0, R0 L1: DSUBIU R3, R2, #2 BNEZ (b2) R3, L2 DADD R2, R0, R0 L2: DSUBU R3, R1, R2 BEQZ (b3) R3, L3 if (aa == 2) aa = 0; if (bb == 2) bb = 0; if (aa != bb) MIPS code CSCE 614 Fall 2009

  9. Correlating Predictors (Two-Level Predictors) • The behavior of b3 is correlated with the behavior of b1 and b2. • b1: not taken and b2: not taken => b3: taken • Branch predictors that use the behavior of other branches to make a prediction CSCE 614 Fall 2009

  10. Correlating Predictors • Two-level predictors BNEZ (b1) R1, L1 DADDIU R1, R0, #1 L1: DADDIU R3, R1, #-1 BNEZ (b2) R3, L2 … L2: if (d == 0) d = 1; if (d == 1) CSCE 614 Fall 2009

  11. Assume d = 0, 1, or 2 CSCE 614 Fall 2009

  12. 1-bit Predictor (Initialized to NT) CSCE 614 Fall 2009

  13. (1,1) Predictor • Every branch has two separate prediction bits. • First bit: the prediction if the last branch in the program is not taken. • Second bit: the prediction if the last branch in the program is taken. • Write the pair of prediction bits together. CSCE 614 Fall 2009

  14. Combinations & Meaning CSCE 614 Fall 2009

  15. (1,1) Predictor CSCE 614 Fall 2009

  16. (m,n) Predictor • Uses the last m branches to choose from 2m branch predictors, each of which is an n-bit predictor. • Yields higher prediction rates than 2-bit scheme • Requires a trivial amount of additional hardware • The global history of the most recent m branches are recorded in an m-bit shift register. CSCE 614 Fall 2009

  17. CSCE 614 Fall 2009

  18. (m,n) Predictor • Total number of bits: = 2m x n x #prediction entries selected by the branch address • Examples CSCE 614 Fall 2009

  19. CSCE 614 Fall 2009

  20. Tournament Predictors • Most popular form of multilevel branch predictors • By using multiple predictors (one based on global information, one based on local information, and combining them with a selector), it can select the right predictor for the right branch. • Alpha 21264 • Uses most sophisticated branch predictor as of 2001. CSCE 614 Fall 2009

  21. Tournament Predictors CSCE 614 Fall 2009

  22. CSCE 614 Fall 2009

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