Meenakshi Kaul, Vinoo Srinivasan, Sriram Govindarajan, Iyad Ouaiss, and Ranga Vemuri Ranga.Vemuri@uc.edu University of

1. Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System Meenakshi Kaul, Vinoo Srinivasan, Sriram Govindarajan, Iyad Ouaiss, and Ranga Vemuri Ranga.Vemuri@uc.edu University of Cincinnati http://www.ececs.uc.edu/~ddel/sparcs.html

2. Target Architecture Macro-Library Behavior Spec. Constraints Pre-Processor Temporal Partitioning Estimates Based on Light-Weight High-Level Synthesis Spatial Partitioning Estimates Based on Light-Weight Layout Synthesis High-Level Synthesis RTL design+ Floorplan SPARCS Core Logic/Layout Synthesis Bitmap files Multi-FPGA board Reconfiguration Schedule HOST SPARCS System

3. CONFIGURATIONMEMORY(ROM) SHARED MEMORY (RAM) LOCAL MEMORY FPGA LOCAL MEMORY FPGA INTERCONNECTION NETWORK LOCAL MEMORY FPGA LOCAL MEMORY FPGA INPUTS OUTPUTS SPARCS Goal Binding Specification Architecture memory segment design task I/O M1 T1 T2 dependency channel T3 M2 channel M3 T4 M4 I/O environment task

4. Configure Execute T1 T2 T3 T4 Temporal Partitioning: Goal • Map tasks to temporal partitions. • Map tasks to design points. • Latency minimization. Reconfiguration Schedule 1 T1 T2 T1 T2 2 T3 T3 3 T4 T4 TASK GRAPH TEMPORAL PARTITIONS DESIGN POINTS FOR TASKS

5. Beh. Specification Architecture Constraints High-Level Synthesis Estimator Tool Partition Bounds Estimator Preprocessing Unit <Min. P …Max. P> N = Min. P Latency Bounds Estimator for N partitions Linear Programming Model Relax Number of Partitions (N= N+1) Reduce Latency Bounds Solve for Constraint Satisfaction YES Solution Found? No Is N < Max.P YES Stop Temporal Partitions Temporal Partitioning: Approach

6. Partitioning of the tasks with FPGA mapping T1, T2 T3 T4,T5 FPGA1 FPGA2 FPGA3 Target Architecture Model, Task dependency Graph, Parameterized Component Library Spatial Partitioning: Goal A unified Specification model that captures Set of tasks, memories and interconnections T = { T1, T2 … T5} M = {M1, M2 … M5} I = { I1, I2 … I10} Spatial Partitioner Partition Cost Evaluator LW High Level Synthesis Partitioning of logical Memories with mapping Interconnect Synthesis M2 M4, M3 M1, T5 LM 1 LM 2 LM 3

7. Genetic Partitioning Create Initial Population of partitions Evaluate current population P M I A S Yes + Cost = + + + Max generations reached Pmax Mmax Imax Amax Smax No Stop constraint satisfying solution found Yes No Evolve next generation (selection, crossover and mutation) Increment Generation Spatial Partitioning: Approach Cost Function Where Amax, Smax, Pmax, Imax, and Mmax represent the area constraint, speed constraint, pin constraint, interconnect constraint, and memory constraint. A, S, P, I, and M are the respective constraint violation values for a given chromosome c

8. High Level Synthesis

9. High Level Synthesis UC’s DSS (Distributed Synthesis System) tailored for SPARCS. • Accepts clock period and FPGA resource constraints. • Layout integration for accurate estimates. • Light-weight mode. • Scheduling • Resolves memory conflicts. • Handles user time constraints. • Design estimation. (rough & quick or accurate & slow) • Controller model • Collection of communicating synchronous FSMs. • Facilitates memory access resolution. • Root FSM generates finish_signal for a task. • Done_signal = AND ( ALL finish_signal)

10. Case Study: JPEG Partial Task Graph of 4x4 DCT JPEG flow

11. Case Study: Results Temporal & Spatial Partitions of 4x4 DCT

12. Case Study: Results Static-JPEG Dynamic-JPEG

13. Case Study: Results