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CSE 502: Computer Architecture

CSE 502: Computer Architecture. SystemVerilog. Adapted from slides by Peter Milder. More Resources. Cannot cover everything in one day You will likely need to look up reference material: SystemVerilog for VHDL Users: http://www.systemverilog.org/techpapers/ date04_systemverilog.pdf

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CSE 502: Computer Architecture

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  1. CSE 502:Computer Architecture SystemVerilog Adapted from slides by Peter Milder

  2. More Resources • Cannot cover everything in one day • You will likely need to look up reference material: • SystemVerilog for VHDL Users: http://www.systemverilog.org/techpapers/date04_systemverilog.pdf • http://www.doulos.com/knowhow/sysverilog/ • http://www.eda.org/sv/SystemVerilog_3.1a.pdf • http://electrosofts.com/systemverilog/operators.html • http://www.cl.cam.ac.uk/teaching/1011/ECAD+Arch/files/SystemVerilogCheatSheet.pdf • http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf Adapted from slides by Peter Milder

  3. Basic Module Setup • Assume: • a, b, c are inputs to module • f is output of module • module is named “mymodule” all ports declared here module mymodule(a, b, c, f); output f; input a, b, c; // Description goes here endmodule declare whichports are inputs,which are outputs Adapted from slides by Peter Milder

  4. Module Instantiation • Just like C++ object instantiation • Module name is analogous to Class name • Inputs/outputs are analogous to constructor arguments module mymodule(a, b, c, f); output f; input a, b, c; module_nameinstance_name(port_connections); endmodule Adapted from slides by Peter Milder

  5. Structural Design • Example: multiplexor • Output equals an input • Which one depends on “sel” module mux(a, b, sel, f); output f; input a, b, sel; logic c, d, not_sel; not gate0(not_sel, sel); and gate1(c, a, not_sel); and gate2(d, b, sel); or gate3(f, c, d); endmodule datatype for describing logical value instantiate gates as above Adapted from slides by Peter Milder

  6. Continuous Assign Statement • Specify behavior with assign statement and bit ops. module mux2(a, b, sel, f); output f; input a, b, sel; logic c, d; assign c = a & (~sel); assign d = b & sel; assign f = c | d; endmodule Adapted from slides by Peter Milder

  7. Procedural Statement • Can specify behavior of combinational logic procedurally using always_comb block module mymodule(a, b, c, f); output f; input a, b, c; always_comb begin // Combinational logic described in // C-like syntax end endmodule Adapted from slides by Peter Milder

  8. Procedural Behavioral Mux Description module mux3(a, b, sel, f); output logic f; input a, b, sel; always_comb begin if (sel == 0) begin f = a; end else begin f = b; end end endmodule If we are going to drive f this way, need to declare it as logic Important: for behavior to be combinational, every output (f) must be assigned in all possible control paths Why? Otherwise, would be a latch Adapted from slides by Peter Milder

  9. Condensed if-then-else Form • Syntax borrowed from C: • So, we can simplify the mux: • Or even skip the always_comb block: if (a) b = c; else b = d; same as b = (a) ? c : d; ... always_combbegin f = (sel) ? b : a; end ... assign f = (sel) ? b : a; Adapted from slides by Peter Milder

  10. Accidental Latch Description module bad(a, b, f); output logic f; input a, b; always_comb begin if (b== 1) begin f = a; end end endmodule • This is not combinational, because for certain values of b, f must remember its previous value. • This code describes a latch. (If you want a latch, you should define it using always_latch) • Don’t do this! Adapted from slides by Peter Milder

  11. Multiply-Assigned Values module bad2(...); ... always_comb begin b = ... something ... end always_comb begin b = ... something else ... end endmodule • Both of these blocks execute concurrently • So what is the value of b?We don’t know! • Don’t do this! Adapted from slides by Peter Milder

  12. Multi-Bit Values • Can define inputs, outputs, or logic with multiple bits module mux4(a, b, sel, f); output logic [3:0] f; input [3:0] a, b; input sel; always_comb begin if (sel == 0) begin f = a; end else begin f = b; end end endmodule Adapted from slides by Peter Milder

  13. Multi-Bit Constants and Concatenation • Can give constants with specified number bits • In binary or hexadecimal • Can concatenate with { and } • Can reverse order (to index buffers left-to-right) logic [3:0] a, b, c; logic signed [3:0] d; logic [1:0] e, f; assign a = 4’b0010; // fourbits, specified in binary assign b = 4’hC; // four bits, specified in hex == 1100 assign c = 3; // == 0011 assign d = -2; // 2’s complement == 1110 as bits assign e = {a, b}; // concatenate == 0010_1100 assign f = a[2 : 1]; // two bits from middle == 01 assign g = b[c +: 2]; // two bits from bit c == 11 Adapted from slides by Peter Milder

  14. Case Statements and “Don’t-Cares” module newmod(out, in0, in1, in2); input in0, in1, in2; output logic out; always_comb begin case({in0, in1, in2}) 3'b000: out = 1; 3'b001: out = 0; 3'b010: out = 0; 3'b011: out = x; 3'b10x: out = 1; default: out = 0; endcase end endmodule output value is undefined in this case Last bit is a “don’t care” -- this line will be active for 100 OR 101 default gives “else” behavior. Here active if 110 or 111 Adapted from slides by Peter Milder

  15. Arithmetic Operators • Standard arithmetic operators defined: + - * / % • Many subtleties here, so be careful: • four bit number + four bit number = five bit number • Or just the bottom four bits • arbitrary division is difficult Adapted from slides by Peter Milder

  16. Addition and Subtraction • Be wary of overflow! • Use “signed” if you want values as 2’s complement logic [3:0] a, b; logic [4:0] c; assign c = a+b; logic [3:0] d, e, f; assign f= d + e; 4’b1000 + 4’b1000 = … In this case, overflows to zero Five bit output can prevent overflow: 4’b1000 + 4’b1000 gives 5’b10000 logic signed [3:0] g, h, i; logic signed [4:0] j; assign g = 4’b0001; // == 1 assign h = 4’b0111; // == 7 assign i = g – h; assign j = g – h; i == 4’b1010 == -6 j == 5’b11010 == -6 Adapted from slides by Peter Milder

  17. Multiplication • Multiply k bit number with m bit number • How many bits does the result have? • If you use fewer bits in your code • Get least significant bits of the product logic signed [3:0] a, b; logic signed [7:0] c; assign a = 4'b1110; // -2 assign b = 4'b0111; // 7 assign c = a*b; k+m c = 8’b1111_0010 == -14 logic signed [3:0] a, b, d; assign a = 4'b1110; // -2 assign b = 4'b0111; // 7 assign d = a*b; d = 4’0010 == 2 Underflow! Adapted from slides by Peter Milder

  18. Sequential Design • Everything so far was purely combinational • Stateless • What about sequential systems? • flip-flops, registers, finite state machines • New constructs • always_ff @(posedgeclk, …) • non-blocking assignment <= Adapted from slides by Peter Milder

  19. Edge-Triggered Events • Variant of always block called always_ff • Indicates that block will be sequential logic (flip flops) • Procedural block occurs only on a signal’s edge • @(posedge …) or @(negedge …) always_ff@(posedgeclk, negedgereset_n) begin // This procedure will be executed // anytime clk goes from 0 to 1 // or anytime reset_n goes from 1 to 0 end Adapted from slides by Peter Milder

  20. Flip Flops (1/3) • q remembers what d was at the last clock edge • One bit of memory • Without reset: module flipflop(d, q, clk); input d, clk; output logic q; always_ff @(posedgeclk) begin q <= d; end endmodule Adapted from slides by Peter Milder

  21. Flip Flops (2/3) • Asynchronous reset: module flipflop_asyncr(d, q, clk, rst_n); input d, clk, rst_n; output logic q; always_ff @(posedgeclk, negedgerst_n) begin if (rst_n == 0) q <= 0; else q <= d; end endmodule Adapted from slides by Peter Milder

  22. Flip Flops (3/3) • Synchronous reset: module flipflop_syncr(d, q, clk, rst_n); input d, clk, rst_n; output logic q; always_ff @(posedgeclk) begin if (rst_n == 0) q <= 0; else q <= d; end endmodule Adapted from slides by Peter Milder

  23. Multi-Bit Flip Flop module flipflop_asyncr(d, q, clk, rst_n); input [15:0] d; input clk, rst_n; output logic [15:0] q; always_ff @(posedgeclk, negedgerst_n) begin if (rst_n == 0) q <= 0; else q <= d; end endmodule Adapted from slides by Peter Milder

  24. Parameters • Parameters allow modules to be easily changed • Instantiate and set parameter: module my_flipflop(d, q, clk, rst_n); parameter WIDTH=16; input [WIDTH-1:0] d; input clk, rst_n; output logic [WIDTH-1:0] q; ... endmodule default value set to 16 uses default value my_flipflop f0(d, q, clk, rst_n); changes parameter to12 for this instance my_flipflop #(12) f0(d, q, clk, rst_n); Adapted from slides by Peter Milder

  25. Non-Blocking Assignment a <= b; • <= is the non-blocking assignment operator • All left-hand side values take new values concurrently • This models synchronous logic! always_ff @(posedgeclk) begin b <= a; c <= b; end c gets the old value of b, not value assigned just above Adapted from slides by Peter Milder

  26. Non-Blocking vs. Blocking • Use non-blocking assignment <= to describeedge-triggered (synchronous) assignments • Use blocking assignment = to describecombinational assignment always_ff @(posedgeclk) begin b <= a; c <= b; end always_comb begin b = a; c = b; end Adapted from slides by Peter Milder

  27. Design Example • Let’s say we want to compute f = a + b*c • b and c are 4 bits, a is 8 bits, and f is 9 bits • First, we will build it as a combinational circuit • Then, we will add registers at its inputs and outputs Adapted from slides by Peter Milder

  28. Finite State Machines (1/2) • State names • Output values • Transition values • Reset state Adapted from slides by Peter Milder

  29. Finite State Machines (2/2) • What does an FSM look like when implemented? • Combinational logic and registers(things we already know how to do!) Adapted from slides by Peter Milder

  30. Full FSM Example (1/2) module fsm(clk, rst, x, y); input clk, rst, x; output logic [1:0] y; enum { STATEA=2'b00, STATEB=2'b01, STATEC=2'b10, STATED=2'b11 } state, next_state; // next state logic always_comb begin case(state) STATEA: next_state = x ? STATEB : STATEA; STATEB: next_state = x ? STATEC : STATED; STATEC: next_state = x ? STATED : STATEA; STATED: next_state = x ? STATEC : STATEB; endcase end // ... continued on next slide Adapted from slides by Peter Milder

  31. Full FSM Example (2/2) // ... continued from previous slide // register always_ff @(posedgeclk) begin if (rst) state <= STATEA; else state <= next_state; end always_comb begin // Output logic case(state) STATEA: y = 2'b00; STATEB: y = 2'b00; STATEC: y = 2'b11; STATED: y = 2'b10; endcase end endmodule Adapted from slides by Peter Milder

  32. Multi-Dimensional Arrays modulemultidimarraytest(); logic [2:0][3:0] myarray; assignmyarray[0] = 4'b0010; assignmyarray[1][3:2] = 2'b01; assignmyarray[1][1] = 1'b1; assignmyarray[1][0] = 1'b0; assign myarray[2][3:0] = 4'hC; initial begin $display("myarray == %b", myarray); $display("myarray[2:0] == %b", myarray[2:0]); $display("myarray[1:0] == %b", myarray[1:0]; $display("myarray[1] == %b", myarray[1]); $display("myarray[1][2] == %b", myarray[1][2]); $display("myarray[2][1:0] == %b", myarray[2][1:0]); end endmodule Adapted from slides by Peter Milder

  33. Memory (Combinational read) modulemymemory(clk, data_in, data_out, r_addr, w_addr, wr_en); parameter WIDTH=16, SIZE=256, LOGSIZE=8; input [WIDTH-1:0] data_in; outputlogic [WIDTH-1:0] data_out; inputclk, wr_en; input [LOGSIZE-1:0] r_addr, w_addr; logic [SIZE-1:0][WIDTH-1:0] mem; assigndata_out = mem[r_addr]; always_ff@(posedgeclk) begin mem<= mem; if(wr_en) mem[w_addr] <= data_in; end endmodule Combinational read Default: memory does not change Synchronous write Adapted from slides by Peter Milder

  34. Memory (Synchronous read) module mymemory2(clk, data_in, data_out, r_addr, w_addr, wr_en); parameter WIDTH=16, SIZE=256, LOGSIZE=8; input [WIDTH-1:0] data_in; outputlogic [WIDTH-1:0] data_out; inputclk, wr_en; input [LOGSIZE-1:0] r_addr, w_addr; logic [SIZE-1:0][WIDTH-1:0] mem; always_ff@(posedgeclk) begin data_out <= mem[r_addr]; mem<= mem; if(wr_en) mem[w_addr] <= data_in; end endmodule Synchronous read What happens if we try to read and write the same address? Adapted from slides by Peter Milder

  35. Assertions • Assertions are test constructs • Automatically validated as design as simulated • Written for properties that must always be true • Makes it easier to test designs • Don’t have to manually check for these conditions Adapted from slides by Peter Milder

  36. Example: A good place for assertions • Imagine you have a FIFO queue • When queue is full, it sets status_full to true • When queue is empty, it sets status_empty to true • When status_full is true, wr_en must be false • When status_empty is true, rd_en must be false Adapted from slides by Peter Milder

  37. Immediate Assertions • Checks an expression when statement is executed • Example: assertion_name: assert(expression) pass_code; else fail_code; always @(posedgeclk) begin assert((status_full == 0) || (wr_en == 0)) else $error("Tried to write to FIFO when full."); end Use $display to print text, or $error to print an error message, or $fatal to print an error message and halt simulation Adapted from slides by Peter Milder

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