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The clock

The clock. Clocking Issues. Clock Skew Gating the clock Section 8.8 of text. Clock Skew. A definition – The difference in the arrival time of the clock at different devices. What gives rise to clock skew?. Clock Skew parameters. For proper operation

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The clock

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  1. The clock ECE 561 - Lecture

  2. Clocking Issues • Clock Skew • Gating the clock • Section 8.8 of text ECE 561 - Lecture

  3. Clock Skew • A definition – The difference in the arrival time of the clock at different devices. • What gives rise to clock skew? ECE 561 - Lecture

  4. Clock Skew parameters • For proper operation • tffpd(min) + tcomb(min) – thold – tskew(max) > 0 • Where • tffpd(min)-the propagation delay of F/F clk->Q • tcomb(min) –the time for the combinational logic of the F/F • Thold –the hold time of the F/F • tskew(max) –the clock skew. Note that it subtracts from the hold time margin ECE 561 - Lecture

  5. Best to buffer the clock • Take input clock into buffers that have less load then the entire chip/circuit ECE 561 - Lecture

  6. Gating the clock • When some elements of the circuit need to be sensitive at times and ignore the clock at others • A simple AND gate approach • Can produce glitches • Causes excessive skew ECE 561 - Lecture

  7. Preferred gating the clock • This is a method that addresses the disadvantages of a simple AND gate. ECE 561 - Lecture

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