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Amdahl’s Law in the Multicore Era

ECE 259 / CPS 221 Advanced Computer Architecture II. Amdahl’s Law in the Multicore Era. Mark D.Hill & Michael R.Marty 2008. Presenter : Tae Jun Ham 2012. 1. 17. Outline. Summary - Amdahl’s law in the multicore era - Symmetric MC Case - Asymmetric MC Case - Dynamic MC Case

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Amdahl’s Law in the Multicore Era

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  1. ECE 259 / CPS 221 Advanced Computer Architecture II Amdahl’s Law in the Multicore Era Mark D.Hill & Michael R.Marty 2008 Presenter : Tae Jun Ham 2012. 1. 17

  2. Outline • Summary -Amdahl’s law in the multicore era - Symmetric MC Case - Asymmetric MC Case - Dynamic MC Case • Review - Strong Point - Negative Point - Possible Questions

  3. Problem • Multicore Chip Design has additional degree of freedom • Total number of Cores • Complexity of the individual core • Multicore Chip Design Style (Symmetric / Asymmetric / Dynamic) • Goal of this paper : To explore the design space of multicore chip and obtaining some useful implication for computer architects

  4. Amdahl’s Law • Original : • Multicore :

  5. Basic Assumptions • Limited Resource : Area • Resource Unit : BCE(Base Core Equivalence) • Simple Core : Consume : 1 BCE Performance : 1 • Complex Core : Consume :r BCEs Performance : perf(r) = sqrt(r)

  6. Symmetric Multicore Model • Resource : n BCEs • Each core consumes r BCEs • Total number of core : n/r • Serial Performance : perf(r) • Parallel Performance : perf(r) * (n/r)

  7. Symmetric Multicore Analysis • Parallelization is important • rBCEs>1 can be optimal (Complex core is still important even with the diminishing return in performance per area)

  8. Asymmetric Multicore Model • Resource : n BCEs • One complex core consumes r BCEs • Other cores consumes 1 BCE • Total number of core : n-r+1 • Serial Performance : perf(r) • Parallel Performance : perf(1) * (n-r)+perf(r)

  9. Asymmetric Multicore Analysis • Asymmetric multicore allows better speedups • For asymmetric multicore, having a nice complex core is crucial

  10. Dynamic Multicore Model • Resource : n BCEs • Forms a r BCEs complex core for sequential operation • Other part consumes 1 BCE • Total number of core : n ( parallel ) / n-r+1 (serial) • Serial Performance : perf(r) • Parallel Performance : n * perf(1) = n

  11. Dynamic Multicore Analysis • Dynamic Multicore provides better speedups

  12. Strength • Identified the future research direction • Increase Parallelism • Increase Core Performance • Better asymmetric & dynamic multicore design • Derived corollary for Amdahl’s law for multicore cases

  13. Limitation • Not very accurate model • Limited Resource : combination of power, area and cost • Performance Model : can be different from sqrt(r) • Need to consider partially parallel portion • Skepticism • Can Moore’s law continue till 256 core per chip? • Can we really achieve 99.9% parallelization? • Optimal point highly depends on parallel portion. As parallel portion differs among applications, it is hard to determine the best hardware design

  14. Future work / Discussions • What would be the appropriate ways to implement dynamic multicore design with HW? • How do we develop a better analytical model for multicore performance? • What would be software challenges for asymmetric multicore or dynamic multicore? • What would be the most power efficient multicore design among three choices presented?

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