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REGISTER MANAGMENT TOOL

REGISTER MANAGMENT TOOL. Final presentation – Part A. Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 12/11/2012 Duration: T wo Semesters. Many teams need to create their own register blocks for FPGA systems. Leading to. BUGS. Double Effort. The Solution

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REGISTER MANAGMENT TOOL

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  1. REGISTER MANAGMENT TOOL Final presentation – Part A Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 12/11/2012 Duration: Two Semesters

  2. Many teams need to create their own register blocks for FPGA systems. Leading to BUGS Double Effort The Solution a Register Management Tool Automatically generates registers according to a required specification using a smart interface!

  3. AutoReg – a smart register management tool Insert your project’s specifications to the GUI Automatically create VHD and HSID for register blocks!

  4. The Solution – a Register Management Tool Project Goals • Automatically generates registers according to the required • specification. • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. • Enables REUSE • Creates unity in the registers VHD files • Saves money and resources

  5. The Solution – a Register Management Tool Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. • Creates documentation for the components created • Leads to an organized –HSID • Alarms in case of incorrect input • Manages the registers through the entire project

  6. Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user.

  7. Project Specifications • 1. Writing a GUI interface through which the user will determine a variety of attributes. • 2. Interactivity - The tool will provide feedbackfor user errors and will provide a summary output. VHD files Local Bus Master Simulation Environment • 3. VHDL: • 4. No special license will be needed to operate the tool, an EXE file will be given to the user. • 5. HSID will be generated under IEEE standards (IP-XACT)

  8. Project Steps • 1. Determine the implementation platform of the user • interface and data processing: Excel/MATLAB/C++/C#/JAVA . • 2. Full characterization of the tool capabilities. • 3. Learning the working environment (Wishbone protocol, • advanced VHDL coding , MODELSIM simulation environment). • 4. VHDL generic design and simulation. • 5. Implementing the GUI (Graphic User Interface) • 6. Implementing Automatic VHDL generation. • 7. Final MODELSIM and MATLAB Simulations.

  9. VHDL Implementation

  10. General Description Project Goals • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Register Register Register Block Block Local Bus Register access Block Chip data I/O

  11. VHDL Top Architecture Project Goals Block A reset clk Block_A_reg_top • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Function_1 Reg_status_1 Function_2 Reg_enable_2 Wishbone Master Function_3 func_err_3

  12. Reg Block Architecture Functional Block Block_A_reg_top Inputs from block • Determine and characterize a local bus for communication with all the register slave blocks. • Generic Implementation that allows reuse in multiple projects. • Encapsulation of implementation, which will be hidden from the user. Reg1 WB Slave WB Master Outputs to block Reg2 Priority Encoder Reg3 4 reg_chosen Reg4 Data from chosen register

  13. Wishbone - open source protocol Block A WB Master clk_i cyc_i stb_i adr_i Block B dat_i we_i dat_o ack_o Stall_o Block C

  14. Wishbone Slave Component Idle wr_en=‘0’ rd_en=‘0’ (wbs_cyc_i )●(wbs_stb_i) (wbs_cyc_i )●(wbs_stb_i) Active Cycle wbs_stall_o=‘1’ wbs_we_i Read Cycle rd_en=‘1’ Write Cycle wr_en=‘1’ wbs_we_i gen_reg WB Slave Functional Block dout_valid din_ack Cycle Finished wbs_ack_o=‘1’ wbs_cyc_i

  15. gen_reg Component Idle reg_chosen=‘0 din_ack=‘0’ dout_valid=‘0’ addr==reg addr gen_reg WB Slave Functional Block addr==reg addr addr==reg addr addr==reg addr The Register is chosen reg_chosen=‘1’ Write action Read action rd_en wr_en Register type is W/RW Register type is R/COR/CONST Register type is R/RW/COR/CONST Register type is W Valid Read Action dout_valid=‘1’ Invalid write Action din_ack=‘0’ Valid Write Action din_ack=‘1’ Invalid Read Action dout_valid=‘0’

  16. Generic Implementation

  17. Generic Implementation

  18. VHDL Simulation

  19. Simulation Environment Macro Scripts

  20. Simulation Environment Test Bench Macro Scripts • Compilation • Simulation • Waveforms

  21. Simulation Environment Results Output File Simulation input Simulation outputs Test Bench Macro Scripts Waveforms • Procedure called serially many times • Comparison to expected values • Reporting results to output file • Compilation • Simulation • Waveforms

  22. Test Plan - Overview • Testing small modules separately • gen_reg.vhd: • Read • Write • Read/Write • Clear On Read • Const. • wbs_reg.vhd • Read transactions (single/burst) • Write transactions (single/burst) • encoder_generic.vhd • Then, testing the entire design • Gen_block.vhd

  23. Test Plan – Cases • Testing Regular Activity • Various generic values for address width • Various values for data • Read/Write single/burst wishbone cycles for suitable registers • Testing system boundaries • Testing system generics

  24. Examples – Write and Read register simulation Functional Block addr = 0010 COR WB slave WB Master Legal addr. + Legal operation = Request granted! . . . . Encoder Write Request ‘00001101’ “00000000” “00001101” 4 reg_chosen addr = 1110 W/R

  25. Examples – Write and Read register simulation Functional Block addr = 0010 COR WB slave WB Master Legal addr. + Legal operation = Request granted! . . . . Encoder Read request “00001101” 4 Reg_chosen addr = 1110 W/R

  26. Examples – Write and Read register simulation Functional Block addr = 0010 COR WB slave WB Master . . . . Encoder Data from Register 4 Reg_chosen addr = 1110 W/R

  27. Examples – Write and Read register simulation din = 7 and then 8 wr_en = ‘1’ for 2 cycles Scenario: WB master writes 7 then 8 to register

  28. Examples – Write and Read register simulation din_ack = ‘1’ for 2 cycles dout = 7 and then 8 Results – request is legal! updated data from WB master is transferred to register din_ack rises, indicating dout is updated Register not influenced by data from block (reg_in_b)

  29. Examples – Write and Read register simulation addr = 10 Dout_valid = ‘1’ rd_en = ‘1’ Scenario: WB master tries to read from this register’s address (register address is 10) Also a leglal request! Result: dout_valid rises to ‘1’

  30. Examples – Write and Read register simulation addr = 15 Dout_valid = ‘0’ rd_en = ‘1’ Scenario: WB master tries to read from a different register address Not a legal requst! Result: dout_valid is ‘0’ indicating data is not valid for the current cycle

  31. Examples - Clear On Read register simulation Register written with ‘0’ “00000000” “00000000” Functional Block addr = 0010 COR WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  32. Examples - Clear On Read register simulation Register written with ‘1’ “00010000” “00010000” Functional Block addr = 0010 COR WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  33. Examples - Clear On Read register simulation Block clears input Register is not cleared until it is read “00010000” “00000000” Functional Block addr = 0010 COR Read Request WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  34. Examples - Clear On Read register simulation Register is cleared “00000000” “00000000” Functional Block addr = 0010 COR Register is read WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  35. Graphical User Interface

  36. Requirements from GUI • Easy to use user experience • Feedback is provided in real time • Data is filled automatically if possible • Easy project view and management • Data and Address can be represented in both Hexadecimal and Decimal formats

  37. Opening Screen – project settings Settings made for the entire project Browser for finding the requested directory Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files

  38. Opening Screen – project settings Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Continue to next screen

  39. 2nd Screen – Edit Block settings Settings made for the specific block Opens text editor Specify a name Provide a description (optional)

  40. 2nd Screen – Edit Block settings Settings made for the specific block Specify a name Provide a description (optional) Specify an initial address Specify number of registers choose reset polarity Navigation tree view delete current block Continue to next screen back to project settings

  41. 3rd screen – Edit register settings Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value Back to block settings delete current register Navigation tree view

  42. 3rd screen – Edit register settings Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value

  43. Top menus • File menu Create a new project Open an existing project Save project as Save current project Close current project Exit AutoReg • Help menu About AutoReg Open user guide • Generate menu Generate VHDL files Report for errors

  44. Tree View • “Top View” of the entire project • Automatically sorted by the absolute address • Allows easy navigation between all the screens and components • Addresses and names are filled automatically • Navigation is blocked when errors or missing data is found in the current window

  45. Tree View • Easy to use user experience • Data is filled automatically if possible • Easy project view and management

  46. Errors Display AutoReg notifies the user and prevents access to some contents in the project whenever: Addresses/bits are overlapping Before Deleting an object Data isn’t legal/valid/complete 1. Names must be valid VHDL names 2. Addresses and data must be positive numbers within the user-determined range 3. Some necessary inputs is missing or invalid data was inserted

  47. Errors Display AutoReg notifies the user and prevents access to some contents in the project whenever: Addresses/bits are overlapping Before Deleting an object Data isn’t legal/valid/complete 1. Addresses/ names must not overlap 2. Bits defined under “Special bits” must not overlap

  48. Errors Display AutoReg notifies the user and prevents access to some contents in the project whenever: Addresses/bits are overlapping Before Deleting an object Data isn’t legal/valid/complete 1. User is prompt to save changes before exiting the project 2. User is prompt “Are you sure?” before deleting a block or a register

  49. Errors Display AutoReg notifies the user and prevents access to some contents in the project whenever: Addresses/bits are overlapping Before Deleting an object Data isn’t legal/valid/complete In part B of the project – a conclusive report before generating the VHDL code • Easy to use user experience • Feedback is provided in real time

  50. Conclusions

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