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FPGA Board Introduction and 7-Segment Display Timer Design

Learn FPGA board fundamentals and design a timer using 7-segment display with Quartus II software. Download necessary files, program the FPGA, and implement a clock divider.

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FPGA Board Introduction and 7-Segment Display Timer Design

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  1. FPGA board introduction

  2. Design & Synrhesis software – Quartus II

  3. EP1S25F780C5

  4. Download 7segment_display.rar from 140.113.144.123

  5. Start compilation

  6. Pin assignment

  7. Go to course html 140.113.144.123 • Download reference11 ds_stratix_dsp-board-starter • You should use counter to divide 80MHz clock and make seven segment display a timer to count up 1 number per second.

  8. On board clock

  9. FPGA board overview

  10. Clock pin

  11. Pin of Pushbuttons & Dip Switchs

  12. Pin of Seven segment

  13. Connect JTAG to FPGA board then choose Programmer

  14. Set hardware device

  15. Select USB-blaster then programm.

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