Interrupts-Bus-memory-I/O-Compilers

1. Interrupts-Bus-memory-I/O-Compilers

2. Key Ideas • Interrupts: a way for overlapping the slow I/O execution with the fast processor. • Bus: shared vs. dedicated • If shared, how to resolve the conflict? • Cache Memory: How to time-share a small but fast memory by storing portions of the main memory? • Hashed: Memory address hashed into a fixed location • Random: Store the memory address along side with data (memory add and data pair) • Mixed

3. Interrupts • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing • Program • e.g. overflow, division by zero • Timer • Generated by internal processor timer • Used in pre-emptive multi-tasking • I/O • from I/O controller • Hardware failure • e.g. memory parity error

4. Interrupt Cycle • Added to instruction cycle • Processor checks for interrupt • Indicated by an interrupt signal • If no interrupt, fetch next instruction • If interrupt pending: • Suspend execution of current program • Save context • Set PC to start address of interrupt handler routine • Process interrupt • Restore context and continue interrupted program

5. Instruction Cycle with Interrupts

6. Connecting • All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU

7. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write • Timing

8. Input/Output Connection(1) • Similar to memory from computer’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer

9. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals (control)

10. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts

11. What is a Bus? • A communication pathway connecting two or more devices • Usually broadcast to all devices on the bus • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown

12. Bus Summary • Transfer of data between the CPU & an I/O dev occurs over the bidirectional data bus • The specific I/O dev involved in the transfer is selected via the address bus • The precise timing of the data transfer is determined by the presence of a IN or OUT pulse on the control bus • All three buses participate!

13. Bus Interconnection Scheme

14. Data Bus(What) • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit

15. Address bus (Where) • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. 8080 has 16 bit address bus giving 64k address space

16. Control Bus (When/what to do) • Control and timing information • Memory read/write signal • Interrupt request • Clock signals

17. Control Bus • Control and timing information • Memory read/write signal • I/O read/write signal • Transfer ACK • Bus request • Bus grant • Interrupt request • Interrupt ACK • Clock signals • Reset

18. CPU With Systems Bus

19. Data Flow (Fetch Diagram) 1 2 3b 3c 3b 3a 4 3d

20. Data Flow (Indirect Diagram) 2 3b 3c 3a 3a 1 3d

21. Memory Characteristics • Location • Capacity • Unit of transfer • Access method • Performance • Physical type • Physical characteristics • Organisation

22. Memory Location • CPU • Internal • External

23. Memory Types • RAM Random access memory (processes can access data in any order) • DRAM dynamic RAM requires refresh cycles • SRAM Static RAM no refresh required

24. Memory Capacity • Word size • The natural unit of organization • Number of words • or Bytes

25. Memory Unit of Transfer • Internal • Usually governed by data bus width • External • Usually a block which is much larger than a word • Addressable unit • Smallest location which can be uniquely addressed • Word internally • Cluster on M$ disks

26. Memory Access Methods (1) • Sequential • Start at the beginning and read through in order • Access time depends on location of data and previous location • e.g. tape • Direct • Individual blocks have unique address • Access is by jumping to vicinity plus sequential search • Access time depends on location and previous location • e.g. disk

27. Memory Access Methods (2) • Random • Individual addresses identify locations exactly • Access time is independent of location or previous access • e.g. RAM • Associative • Data is located by a comparison with contents of a portion of the store • Access time is independent of location or previous access • e.g. cache

28. Memory Hierarchy • Registers • In CPU • Internal or Main memory • May include one or more levels of cache • “RAM” • External memory • Backing store

29. Memory Hierarchy - Diagram

30. Performance • Access time • Time between presenting the address and getting the valid data • Memory Cycle time • Time may be required for the memory to “recover” before next access • Cycle time is access + recovery • Transfer Rate • Rate at which data can be moved

31. Physical Types • Semiconductor • RAM • Magnetic • Disk & Tape • Optical • CD & DVD • Others • Bubble • Hologram

32. Physical Characteristics • Decay • Volatility • Erasable • Power consumption

33. The Bottom Line • How much? • Capacity • How fast? • Time is money • How expensive?

34. Hierarchy List • Registers • L1 Cache • L2 Cache • Main memory • Disk cache • Disk • Optical • Tape

35. So you want fast? • It is possible to build a computer which uses only static RAM • This would be very fast • This would need no cache • How can you cache cache? • This would cost a very large amount

36. Compilers • Machine language • Assemblers • High Level lanuages

37. Machine Language • Only language the HW understands • “Natural language” • Machine dependent • Incomprehensible to humans • Hard addressing, no variables. • 1300042774 (basepay) • 1400059341 (add OT) • 1200274027 (store grosspay)

38. Assemblers • Uses English like abbreviations • Translator convert assembler programs into machine language • Clearer to humans, uses variables • LOAD BASEPAY • ADD OVERTIME • STORE GROSSPAY

39. High level languages • Fortran • Cobol • Basic • Pascal • C • Java

40. Compiling • Compile - parses source code for syntax • Linking – integrating external modules into the executable program, symbol table • Loading – address binding

41. The Next Step - RISC • Reduced Instruction Set Computer • Key features • Large number of general purpose registers • or use of compiler technology to optimize register use • Limited and simple instruction set • Emphasis on optimising the instruction pipeline

42. RISC Characteristics • One instruction per cycle • Register to register operations • Few, simple addressing modes • Few, simple instruction formats • Hardwired design (no microcode) • Fixed instruction format • More compile time/effort