Resilient Circuits for Dynamic Variation Tolerance

1. 1

2. 2

3. 3

4. 4

5. 5

6. 6

7. 7

8. 8 (1) Transition detector senses input data transitions during the high clock phase. If input data arrives late, the error signal dynamically rises. (2) Since min-delay paths are designed with sufficient margin, the master latch of a datapath flip-flop is unnecessary. (3)The datapath latch behaves identical to a pulsed-latch, resulting in lower clock energy and eliminating datapath metastability. (4) Although the transition detector may become metastable, this is not critical. (1) Transition detector senses input data transitions during the high clock phase. If input data arrives late, the error signal dynamically rises. (2) Since min-delay paths are designed with sufficient margin, the master latch of a datapath flip-flop is unnecessary. (3)The datapath latch behaves identical to a pulsed-latch, resulting in lower clock energy and eliminating datapath metastability. (4) Although the transition detector may become metastable, this is not critical.

9. 9 (1) Similar to TDTB except a shadow flip-flop replaces the transition detector. (2) Retains the time-borrowing feature of TDTB to eliminate datapath metastability. (3) DSTB clock energy overhead is slightly lower than RFF since a datapath sequential is typically sized larger than a minimum-sized shadow sequential.(1) Similar to TDTB except a shadow flip-flop replaces the transition detector. (2) Retains the time-borrowing feature of TDTB to eliminate datapath metastability. (3) DSTB clock energy overhead is slightly lower than RFF since a datapath sequential is typically sized larger than a minimum-sized shadow sequential.

10. 10

11. 11

12. 12

13. 13

14. 14

15. 15

16. 16

17. 17

18. 18

19. 19

20. 20

21. 21

22. 22

23. 23

24. 24

25. 25

26. 26

27. 27

28. 28

29. 29

30. 30

31. 31

32. 32

33. 33