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Booleanizing Analog Systems for Chip Verification: A New Approach

This paper presents an innovative methodology for verifying chip specifications in analog systems, addressing challenges faced by chip designers. The proposed approach "Booleanizes" analog components to allow for effective verification alongside digital logic. By employing Boolean approximation techniques, we can achieve fast formal verification, high-speed simulation, and test pattern generation for entire systems, such as SERDES and PLLs. Key outcomes include successful Booleanization of various analog components and demonstration of effective verification tools that maintain the integrity of mixed-signal designs.

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Booleanizing Analog Systems for Chip Verification: A New Approach

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  1. ABCD: “Booleanizing” AnalogSystems for Verifying Chips Aadithya V. Karthik, Sayak Ray, PierluigiNuzzo, Alan Mishchenko, Robert Brayton, and JaijeetRoychowdhury EECS Dept., The University of California, Berkeley Feb 2014, BEARS, Berkeley

  2. The Problem: Verifying a Chip Specification Chip designers Chip

  3. The Problem: AMS Verification Want to verify complete system e.g., eye opening height > 1V? Proof or counter-example needed Example: SERDES PLL Analog parts CDR I/O Surrounded by Digital Logic >1V

  4. Our approach: “Booleanize” the analog parts Analog models Challenge: Digital models (don't mix) + ABCD: Boolean approximation ALL BOOLEAN Continuous Boolean Best verification tools = all Boolean, no continuous SAR-ADC Boolean T/H approximation Boolean comparator approximation Boolean DAC approximation Analog components Digital components Verification tools accept Fast Formal verification, high-speed simulation, test pattern generation, ... … for the full combined system!

  5. ABCD in action ABCD Purely Boolean Model Analog Circuit Example: Channel + Equalizer Bit Sequence

  6. Circuits Successfully Booleanized Delay line Charge pump Power grid Equalizer I/O signaling system SAR-ADC

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